MAS9180 Datasheet, PDF (9/15 Pages) Micro Analog systems – AM Receiver IC

DA9180.004
15 September, 2005
MAS9180 SAMPLES IN SBDIL 20 PACKAGE
NC 1
VDD 2
NC 3
QOP 4
QOM 5
NC 6
QI 7
AGC 8
NC 9
OUT 10
20 VSS
19 NC
18 RFIM
17 RFIP
16 NC
15 NC
14 PDN
13 AON
12 DEC
11 NC
Top Marking Definitions:
YYWW = Year Week
XXXXX.X = Lot Number
z=Sample Version Number
PIN DESCRIPTION
Pin Name
Pin
Type
Function
NC
1
VDD
2
P
Positive Power Supply
NC
3
QOP
4
AO
Positive Quartz Filter Output for Crystal
QOM
5
Negative Quartz Filter Output for External
Compensation Capacitor or Second Crystal
NC
6
QI
7
AI
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC
8
AO
AGC Capacitor
NC
9
OUT
10
DO
Receiver Output
NC
11
DEC
12
AO
Demodulator Capacitor
AON
13
DI
AGC On Control
PDN
14
DI
Power Down Input
NC
15
NC
16
RFIP
17
AI
Positive Receiver Input
RFIM
18
AI
Negative Receiver Input
NC
19
VSS
20
G
Power Supply Ground
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Note
5
1
2
3
4
6
6
Notes:
1) Pin 6 between QOM and QI must be connected to VSS to eliminate DIL package leadframe parasitic
capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also
recommended to be connected to VSS to minimize noise coupling.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
- the output is a current source/sink with |I_OUT| > 5 µA
- at power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working)
- Internal pull-up with current < 1 µA which is switched off at power down
4) PDN = VSS means receiver on; PDN = VDD means receiver off
- Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) External crystal compensation capacitor pin QOM is connected only in MAS9190A5 and AF versions. It is left
unconnected in MAS9180A1 and AB..E versions which have internal compensation capacitor.
6) Differential input versions A1..A5 have 600 kΩ biasing MOSFET-transistors towards ground from both
receiver inputs RFIP and RFIM. Asymmetric input versions AB..AF have input pin RFIM unconnected.
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