MT4HTF1664AY Datasheet, PDF (12/19 Pages) Micron Technology – DDR2 SDRAM UDIMM

128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
I_DD Specifications
Table 11: DDR2 I_DD Specifications and Conditions – 256MB
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
Parameter
-80E/
Symbol -800 -667 -53E -40E Units
Operating one bank active-precharge current:^tCK = ^tCK (I_DD), ^tRC =
I_DD0
t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is HIGH, S# is HIGH between valid}
commands; Address bus inputs are switching; Data bus inputs are switching
540 480 440 440 mA
Operating one bank active-read-precharge current: I_OUT = 0mA; BL =
4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRC = ^tRC (I_DD), ^tRAS = ^tRAS MIN
(I_DD), ^tRCD = ^tRCD (I_DD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as I_DD4W
Precharge power-down current: All device banks idle; ^tCK = ^tCK (I_DD);
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
I_DD1
I_DD2P
660 600 540 520 mA
28 28 28 28 mA
Precharge quiet standby current: All device banks idle; ^tCK = ^tCK (I_DD); I_DD2Q 260 220 180 160 mA
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle; ^tCK = ^tCK (I_DD); CKE is I_DD2N 280 240 200 180 mA
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open; ^tCK
= ^tCK (I_DD); CKE is LOW; Other control and address bus in-
puts are stable; Data bus inputs are floating
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
I_DD3P
160 140 120 100 mA
48 48 48 48
Active standby current: All device banks open; ^tCK = ^tCK (I_DD), ^tRAS =
I_DD3N 300 280 240 200 mA
t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between valid com-}
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
I_DD4W 1180 1000 820 640 mA
burst writes; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS MAX
(I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, S# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst I_DD4R 1100 940 780 620 mA
read, I_OUT = 0mA; BL = 4, CL = CL (I_DD), AL = 0; ^tCK = ^tCK (I_DD), ^tRAS = ^tRAS
MAX (I_DD), ^tRP = ^tRP (I_DD); CKE is HIGH, S# is HIGH between valid com-
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:^tCK = ^tCK (I_DD); REFRESH command at every ^tRFC
I_DD5
(I_DD) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
trol and address bus inputs are switching; Data bus inputs are switching
920 740 700 680 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
I_DD6
28 28 28 28 mA
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
12
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