88ALP01 Datasheet, PDF (31/160 Pages) –

2.2.1.1
2.2.1.2
2.2.1.3
Functional Description
Functional Overview
„ Access to the configuration data
„ Access to memory mapped resources
„ PCI bus master operation of 88ALP01
Data transfers via the PCI bus are 4 bytes wide (32 bit). The transfer rate also depends on the bus
clock (0 to 33 MHz / up to 66 MHz).
The BIU handles the basic protocol for accesses via the PCI bus. It is built of several state machines
running synchronously with the PCI bus CLK signal. All inputs are synchronously sampled. All
outputs are synchronously generated on the rising edge of CLK to assure that interrupts are
serviced independently of the PCI clock speed.
The 88ALP01 is a 32-bit device. It is mapped into the lower 4 GB of the address space and therefore
ignores all dual address cycles.
The master section of the BIU is treated in more detail when data transfer over the PCI bus is
discussed. It is not of interest in connection with the programming interface since bus master
operations are performed by the 88ALP01 hardware according to the preconfigured control
registers.
Slave Access to Configuration Space
Slave access to the configuration space is also not of primary interest for the programming interface.
However, it may be valuable for troubleshooting with PCI bus analyzers and exerciser tools. This
bus operation is performed by the target sequencer state machine. Acceptance and termination of a
transaction is determined by a backend consisting of the configuration decoder and the
Configuration Register File.
The adapter responds to type 0 configuration accesses (AD[1:0] = “00”, IDSELn). If the configuration
space is targeted for a burst operation, it responds with a disconnect on the first data transfer.
The Configuration Register File can be accessed with 8-bit, 16-bit, or 32-bit transfers.
Configuration transactions are not aborted (target initiated termination).
On read transactions, all data is driven as defined for full 32-bit accesses independent of CBEn[3:0].
Slave Access to Memory Resources
There is only one accessible resource, the Memory Mapped I/O-Resources.
Accesses to memory mapped I/O-Resources are performed by the target sequencer state machine.
Acceptance and termination of a transaction is determined by a backend consisting of the control
decoder and the control register file.
The control registers have to be accessed with the minimum data width (8-, 16-, or 32-bit) transfers
depending on the definition of the registers.
On read transactions, all data is driven as defined for full 32-bit accesses independently of
CBEn[3:0]. If the memory resources are targeted for a burst operation, the BIU responds with a
disconnect on the first data transfer.
All PCI memory cycles are preset to simple memory read and memory write cycles.
Master Access
The master sequencer state machine is controlled by giving address, guaranteed number of bytes to
be transferred (plus minor additional informations) on a per-cycle basis from one of the three master
backends (queues). If not owner of the PCI bus already, bus is requested.
The BIU releases ownership of the bus for several reasons:
„ Number of bytes to transfer is zero
Copyright © 2007 Marvell
July 17, 2007, Preliminary
Document Classification: Proprietary Information
Doc. No. MV-S103921-00 Rev. –
Page 31