MV78100_1 Datasheet, PDF (1/2 Pages) –

Marvell MV78100 SoC with Sheeva Technology
Discovery Innovation Series
PRODUCT OVERVIEW
The MV78100 is a high-performance, low-power, highly integrated processor with the Marvell^® Sheeva™ CPU technology
included. The Sheeva core is an ARMv5TE-compliant CPU core. Built on Marvell’s innovative Discovery™ system controller
platform, the MV78100 is a complete system-on-chip (SoC) solution. Optimized for low power operation, the MV78100 is
ideally suited to a wide range of applications ranging from sophisticated routers, switches and wireless base stations to
high-volume laser printers applications.
The MV78100 offers unparalleled integration that makes system design simple and cost efficient. The SoC integrates:
• High-performance dual-issue CPU with Vector Floating Point (VFP) support
• 800 MHz, 1 Ghz and 1.2 Ghz operating speed
• 32KB-Instruction and 32KB-Data 4-way, set-associative L1 cache
• 512KB unified 8-way, set-associative L2 cache
• 40/72-bit high bandwidth DDR2 memory interface (up to 800 MHz data rate)
• Two Gigabit Ethernet MACs with interface options
• Two PCI-Express ports (x4 or Quad x1)
• Three USB 2.0 ports with integrated PHYs
• Two SATA 2.0 ports with integrated PHYs
• Security engine
• Pin-compatible with dual-core (MV78200) version
The innovative, on-chip crossbar architecture with any-to-any connectivity enables concurrent transactions among multiple
units that results in high system throughput allowing system designers to create high-performance scalable systems.
Tightly integrated CPU and memory controller significantly improves application performance.
BLOCK DIAGRAM
Sheeva™ CPU Core
Dual Issue w/FPU
32KB-I, 32KB-D
800MHz–1.2GHz
512KB L2
2 x GE
MAC
2 x SATA II
with PHY
3 x USB 2.0
with PHY
System Crossbar
DDR II
Controller
32/64-bit
DDR2-800
with ECC
PCI-E
PCI-E
2 x TDM
channels
x 4 or
quad x 1
Device bus
Security
4 IDMA
NAND ctlr
Engine
+ 2 XOR
4 x UARTs
32b
TWSI, SPI
Fig 1. MV78100 SoC Block Diagram