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88F6190 Datasheet, PDF (1/2 Pages) – | |||
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Marvell 88F6190 SoC with Sheeva Technology
Kirkwood Series
PRODUCT OVERVIEW
The Marvell® 88F6190 SoC with Sheeva⢠embedded CPU technology, is a high-performance integrated controller for value
class applications. It integrates the Marvell Sheeva CPU core which is fully ARMv5TE-compliant with a 256KB L2 Cache. The
88F6190 builds upon Marvellâs innovative Feroceon® family of processors, improves performance, and adds new features
to reduce bill of materials (BOM) costs. The 88F6190 is suitable for a wide range of applications such as routers, gateway,
storage, networking and printer products.
The 88F6190 offers unparalleled integration that makes system design simple and cost efficient. The SoC integrates:
⢠High-performance single-issue CPU
⢠600 Mhz operating speed
⢠16KB-Instruction and 16KB-Data 4-way, set-associative L1 cache
⢠256KB unified 4-way, set-associative L2 cache
⢠16-bit DDR2 memory interface (up to 600 MHz data rate)
⢠Single Gigabit Ethernet and single Fast Ethernet MAC with interface options
⢠Precise Timing Protocol and Audio Video Bridging
⢠Single PCI-Express port
⢠Single USB 2.0 port with integrated PHY
⢠Single SATA 2.0 port with integrated PHY
⢠Network security engine with various encryption algorithm support
⢠SDIO, NAND flash, SPI, TWSI, and Two UART interfaces
The innovative, on-chip crossbar architecture with any-to-any connectivity enables concurrent transactions among multiple
units that results in high system throughput allowing system designers to create high-performance scalable systems.
Tightly integrated CPU and memory controller significantly improves application performance.
BLOCK DIAGRAM
Sheeva⢠CPU Core
Single Issue
16KB-I, 16KB-D
600MHz
256KB L2
DDR II
Controller
1 x GE
1 x FE
MAC
1 x SATA II
with PHY
USB 2.0
with PHY
System Crossbar
PCI-E
SDIO
Security
Engine
4 IDMA/
XOR
NAND Ctlr
2 x UART
TWSI, SPI
Fig 1. 88F6190 SoC Block Diagram
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