MLS9228-01760 Datasheet, PDF (1/2 Pages) Tyco Electronics – Surface Mount Frequency Synthesizer CDMA 1720 - 1800 MHz

Surface Mount Frequency Synthesizer
MLS9228-01760
MLS9228-01760
Surface Mount Frequency Synthesizer
CDMA 1720 - 1800 MHz
Features
12 Lead Package
• Integrated VCO/PLL
• Miniature SMT Package
• Low Phase Noise
• +5V Operation
DETAIL A
12 11 10 9 8 7
M/ A- COM LTD
PART NO.
Description
DATE CODE
The MLS9228-01760 synthesizer design integrates a high perfor-
mance buffered VCO, PLL circuit and discrete loop filter in a
12 34 5 6
surface mount package. The SMT packaging provides electrical
IDENT
0.2
shielding, easy PCB assembly and repeatable performance. The
synthesizer is designed for use in PCS CDMA base stations and is
optimised for coverage of the PCS band with 50 kHz step size and
0.6
low phase noise and spurious.
M/A-COM synthesizers are manufactured in an ISO 9001 certi-
fied facility, incorporating surface mount assembly and automated
electrical testing. This ensures consistent electrical performance
and quality over volume production quantities.
2.0
TYP.in 5 POSITIONS
0.8
1.0
DETAIL A
13.2
Electrical Specifications¹, T_A = +25°C, V_CC = +5V, ∆F = 50 kHz, F_R = 15 MHz (unless otherwise stated)
Parameter
Test Conditions
Units
Min.
Typ.
Max.
Frequency Range (F_OUT)²
RF Output Power (P_OUT)³
Harmonic Output
Over T_OP
Over T_OP
MHz
1720
—-
1800
dBm
-3.0
—-
+3.0
dBc
—-
-15
-10
Spurious Output
Phase Noise⁴
Phase comparison frequency (F_OUT ± ∆F)
Reference breakthrough (F_OUT±F_R)
SSB at 1 kHz offset from carrier
dBc
—-
dBc
—-
dBc/Hz
—-
-75
-60
-75
—-
-70
-65
SSB at 10 kHz offset from carrier
dBc/Hz
—-
-95
-90
SSB at 100 kHz offset from carrier
dBc/Hz
—-
-115
-110
SSB at 1.25 MHz offset from carrier
dBc/Hz
—-
-136
—-
Integrated Phase Noise
300 Hz to 3 kHz bandwidth
mrad rms
—-
26
—-
Frequency Switching Time^5,6
Over F_OUT, measured to within ±500 Hz
ms
—-
35
—-
VCO Supply Current (I_CC1)
mA
—-
19
21
PLL Supply Current (I_CC2)
mA
—-
12
14
VCO Supply Voltage (V_CC1)
Recommended operating limit
V
+4.75
—-
+5.25
PLL Supply Voltage (V_CC2)
Step Size (∆F)⁷
Recommended operating limit
Recommended operating limit
V
+4.75
—-
+5.25
kHz
—-
50
—-
Reference Frequency (F_R)⁸
0.5 to 2.0 Vpp sine wave into a.c. coupled
CMOS. Recommended operating limit
MHz
3
—-
20
1. All specification limits are indicated values and apply over F_OUT and
for 50Ω load impedance.
2. Programming control is 3 wire serial CMOS or TTL levels, in accor-
dance with National Semiconductor LMX 2325.
3. Output power window includes variation over operating temperature
range (T_OP) -40°C to +85°C and output frequency range (F_OUT).
4. See plot for typical phase noise at other frequency offsets.
5. See plot for typical full band switching time measured to within
other offsets from final frequency.
6. Integral PLL lock monitor output, TTL high locked, TTL low un-
locked.
7. Device designed for loop bandwidth of 200 Hz.
8. Reference frequency input impedance 10kΩ min.
V2.00
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M/A-COM Division of AMP Incorporated s North America: Tel. [phone], Fax [phone] s Asia/Pacific: Tel.[phone],
Fax [phone] s Europe: Tel. [phone], Fax[phone]
AMP and Connecting at a Higher Level are trademarks.
Specifications subject to change without notice.