MLS9037-00110 Datasheet, PDF (1/2 Pages) Tyco Electronics – Surface Mount Frequency Synthesizer IF 109 - 111 MHz

Surface Mount Frequency Synthesizer
MLS9037-00110
MLS9037-00110
Surface Mount Frequency Synthesizer
IF 109 - 111 MHz
Features
• Integrated VCO/PLL
• Miniature SMT Package
• Low Phase Noise
• +5V Operation
Description
The MLS9037-00110 synthesizer design integrates a high perfor-
mance buffered VCO, PLL circuit and discrete loop filter in a
surface mount package. The SMT packaging provides electrical
shielding, easy PCB assembly and repeatable performance. The
synthesizer is designed for use in CDMA base stations and is
optimised for 115 MHz IF at the cellular Tx frequency with 20 kHz,
step size and low phase noise.
M/A-COM synthesizers are manufactured in an ISO 9001 certi-
fied facility, incorporating surface mount assembly and automated
electrical testing. This ensures consistent electrical performance
and quality over volume production quantities.
12 Lead Package
12 11 10 9 8 7 ^{DETAIL A}
M/ A- COM LTD
PART NO.
DATE CODE
1234 5 6
IDENT
0.2
2.0
TYP.in 5 POSITIONS
13.2
0.6
0.8
1.0
DETAIL A
Electrical Specifications¹, T_A = +25°C, V_CC = +5V , ∆F = 20 kHz, F_R = 15 MHz (unless otherwise stated)
Parameter
Test Conditions
Units
Min.
Typ.
Max.
Frequency Range (F_OUT)²
RF Output Power (P_OUT)³
Over T_OP
Over T_OP
MHz
109
—
111
dBm
-3.0
—
+3.0
Harmonic Output
—
dBc
—
-35
-20
Spurious Output
Phase comparison frequency (F_OUT ± ∆F)
dBc
—
-85
-70
Phase Noise⁴
Reference breakthrough (F_OUT ± F_R)
SSB at 100 Hz offset from carrier
dBc
—
-95
—
dBc/Hz
—
-73
—
Integrated Phase Noise
Frequency Switching Time^5,6
VCO Supply Current (I_CC1)
PLL Supply Current (I_CC2)
VCO Supply Voltage (V_CC1)
PLL Supply Voltage (V_CC2)
Step Size (∆F)⁷
Reference Frequency (F_R)⁸
SSB at 1 kHz offset from carrier
SSB at 10 kHz offset from carrier
SSB at 100 kHz offset from carrier
300 Hz to 3 kHz bandwidth
Over F_OUT, measured to within ± 500 Hz
—
—
Recommended operating limit
Recommended operating limit
Recommended operating limit
0.5 to 2.0 Vpp sine wave into a.c. coupled
CMOS. Recommended operating limit
dBc/Hz
dBc/Hz
dBc/Hz
mrad rms
ms
mA
mA
V
V
kHz
MHz
—
—
—
—
—
—
—
+4.75
+4.75
—
3
-92
-112
-134
4
30
15
7
—
—
20
—
-85
-107
—
9
—
20
10
+5.25
+5.25
—
20
1. All specification limits are indicated values and apply over F_OUT and
for 50 Ω load impedance.
2. Programming control is 3 wire serial CMOS or TTL levels, in accor-
dance with National Semiconductor LMX 1511.
3. Output power window includes variation over operating temperature
range (T_OP) -40°C to +85°C and output frequency range (F_OUT).
4. See plot for typical phase noise at other frequency offsets.
5. See plot for typical full band switching time measured to within
other offsets from final frequency.
6. Integral PLL lock monitor output, TTL high locked, TTL low
unlocked.
7. Device designed for loop bandwidth of 150 Hz.
8. Reference frequency input impedance 10 kΩ min.
V2.00
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M/A-COM Division of AMP Incorporated s North America: Tel. [phone], Fax [phone] s Asia/Pacific: Tel.[phone],
Fax [phone] s Europe: Tel. [phone], Fax[phone]
AMP and Connecting at a Higher Level are trademarks.
Specifications subject to change without notice.