28960-SWG-001-A Datasheet, PDF (62/105 Pages) M/A-COM Technology Solutions, Inc. – Software Users Guide

Appendix A Command Set Reference
A.1 Control Commands
Bt8960
Software User’s Guide
A.1.6 Data Transfer Format
Selects the format in which data is transferred between the Bt8960 and the application. This option
has no effect on data value, only the data transfer format is affected. Different data transfer formats
allow for different schemes of framer bit-pump clock distribution. For more details, see the Bt8960
datasheet.
Numeric Value
0x06
Opcode
C Constant (defined in file api.h)
_FRAMER_FORMAT
Option
Parallel data,
clock outputs
Parallel data,
clock inputs
Serial data
Serial Swap
data
Options
Description
The Bt8960 supplies a baud rate clock signal (QCLK) that times
the data transfer in both the receive and transmit directions.
Received quats are being transferred to the framer via the
RQ[0], RQ[1] pins. Transmitted quats are being transferred to
the bit-pump via the TQ[0], TQ[1] pins.
A baud rate clock signal (RBCLK) is supplied that times the data
transfer in the receive direction. Also supplied is a separate
baud rate clock (TBCLK) that times the data transfer in the
transmit direction. Received and transmitted quats are
transferred via the TQ and RQ signals, as in “Parallel with clock
outputs” mode. The RBCLK and TBCLK signals must be a
derivative of the Bt8960’s 16X clock at an arbitrary phase.
The Bt8960 supplies a baud rate clock (on the QCLK pin) and a
bit rate clock (on the RQ[0] pin) that time the data transfer in
both receive and transmit directions. The received and
transmitted quats are transferred serially, each on a single line,
via the RQ[1] and TQ[1] pins. The 2B1Q magnitude bit is
aligned to QCLK low and the 2B1Q sign bit is aligned to QCLK
high.
The Bt8960 supplies a baud rate clock (on the QCLK pin) and a
bit rate clock (on the RQ[0] pin) that time the data transfer in
both receive and transmit directions. The received and
transmitted quats are transferred serially, each on a single line,
via the RQ[1] and TQ[1] pins. The 2B1Q magnitude bit is
aligned to QCLK high and the 2B1Q sign bit is aligned to QCLK
low. This format satisfies the ETSI/ANSI requirements for
output quat orientation
Data
Field
0x00
0x01
0x02
0x03
C Constant (api.h)
_PARALLEL_MASTER
_PARALLEL_SLAVE
_SERIAL
_SERIAL_SWAP
A-6
Conexant
100251B
Preliminary Information/Conexant Proprietary and Confidential