M21131 Datasheet, PDF (59/65 Pages) M/A-COM Technology Solutions, Inc. – 72x72/144x144 3.2 Gbps Asynchronous Crosspoint Switch with Amplif-EYE Signal Conditioning

Functional Description
reference input, the PLL output frequency programming is described in “PRBS CDR Control Parameters” on
page 59. Register PLL_CTRLB[7] provides a PLL software reset if required.
4.3.13.2
Additional Test Patterns
The PRBS TX can also output a 0101 or a 0011 pattern. By setting register PRBSTXCTRL2[1] = 1 (default 0) this
mode is selected. If PRBSTXCTRL2[2] = 1 then a 0011 pattern is generated otherwise a 0101 pattern is created
(default).
4.3.13.3
PRBS Output Data
The output data is updated with each rising edge of CLKTXP. The output terminal Trig (CLKTXP/N divided by 16) is
used as a scope trigger to observe the 2²³-1 pattern and can be disabled with Register PRBSTXCTRL2[0 = 0
(default). It is a single ended PCML output with 50Ω on chip source termination and 450 mVp–p single ended
swing into an external 50Ω load.
The PRBS TX data can be observed at terminals DOTXP and DOTXN (PCML output with 50Ω on chip source
termination and 900 mVp–p differential swing into an external 50Ω load) and can be routed internally to any of the
inputs. When routing PRBSTX through the crosspoint core, DOTXP/N needs to be terminated with 50Ω load.
Register PRBSTXCTRL1[2] = 0 disables the PRBS TX output to be routed to any input; with PRBSTXCTRL1[2] = 1
(default).
Register PRBSTXCHSEL[7:0] selects the input to which the PRBS TX will be routed. Input channel N is selected
by setting PRBSTXCHSEL[7:0] = Nh. If an invalid input is selected (N>71/143), then the PRBS TX will not be
routed to any input.
Note that the PRBS TX signal will be forced into the input terminals (the on-chip PRBS buffers are operating in
current mode); a portion of the PRBS signal will egress from the input terminal to which the PRBS transmitter is
connected. The device normally connected to these terminals may need to be powered down (it is acceptable to
have the 50Ω source termination still present) or temporarily disconnected during PRBS operation.
4.3.13.4
PRBS RX Control Parameters
A 2²³-1 PRBS RX takes in a NRZ PRBS pattern (with polynomial D23+D18+1) and checks for any bit errors. The
PRBS RX includes an integrated CDR which uses RXREFCLK as a low-speed reference clock.
The PRBS RX will be enabled with register PRBSRXCTRL[3] = 1 (default 0) or with terminal XENRX = L (CMOS
level, internal pull-up). When enabled, the PRBS RX takes its input directly from any of the odd or even core
outputs as enabled by PRBSRXCTRL[5] = 0, or from external inputs DIRXP/N enabled by PRBSRXCTRL[5] = 1
(default).
Register PRBSRXCTRL[2] = 0 prevents any of the core outputs from being connected to the PRBS RX. If register
PRBSRXCTRL[2] = 1 (default), then PRBSRXCHSEL[7:0] selects which core output channel goes to the PRBS
RX. In either case, the input to the PRBS RX is first routed into a dedicated CDR to resample the data and to
extract a clock for the PRBS RX. Register PRBSRXCTRL[1] = 0 (default 1) enables the CDR.
4.3.13.5
PRBS CDR Control Parameters
Register CDR: RXCDR_CTRLB[6:0] controls the desired bit rate, and CDR: RXCDR_CTRLB[7] provides a means
for a software reset. The CDR must be in lock before valid data can be passed on to the actual PRBS RX circuit.
Register RXCDR_ALARMS[1:0] contain the normal CDR alarms; these bits need to be 0 for the PRBS RX to
produce valid error counts. For this reason the PRBS RX needs to remain in reset while the CDR is acquiring lock.
This can be done by setting register XRSTRX = L (CMOS level, internal pull-up) or with PRBSRXCTRL[4] = 1
(default 0).
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