211X1-DSH-001-I Datasheet, PDF (50/65 Pages) M/A-COM Technology Solutions, Inc. – 72x72/144x144 3.2 Gbps Asynchronous Crosspoint Switch

Functional Description
4.3.3
Serial I/O Overview
The serial I/O operation is gated by chip select signal XCS (on input terminal XCS). Data is shifted in on terminal
SDI on the falling edge of the serial I/O clock input (terminal SCLK), and shifted out on the serial data output
(terminal SDO) on the rising edge of SCLK. Addressing a register consists of the following, as shown in Figure 4-7:
A 12-bit input, consisting of the first bit (start bit, SB = 1), the second bit (operation bit: OP = 1 for read, OP = 0 for
write), followed by the 10-bit address (most significant bit (MSB) first).
Figure 4-7. Serial Word Format
MSB
LSB MSB
LSB
19 18 17
87
0
1 rw
A[9:0]
D[7:0]
Start Bit
Address
Read/Write
Data
4.3.3.1
Timing Diagram Clock Set and Program Modes
To initiate a write sequence, as shown in Figure 4-8, terminal XCS goes low before the falling edge of SCLK. On
each falling edge of serial I/O clock (SCLK) the 20-bit word consisting of SB = 1, OP = 0, address, and data, are
latched into the input shift register. The rising edge of signal XCS must occur before the falling edge of SCLK for
the last bit. Upon receipt of the last bit, one additional cycle of SCLK is necessary before the input data transfers
from the input shift register to the addressed register.
If consecutive read/write cycles are being performed, it is not necessary to insert an extra clock cycle between
read/write cycles, however one extra clock cycle is needed after the last data bit of the final read/write cycle to
complete the operation. On a write cycle, only the first 18 bits after SB and OP are used and all bits that follow are
ignored.
Figure 4-9 illustrates the serial read mode timing diagram. To initiate a read sequence, the signal on terminal XCS
goes low before the falling edge of SCLK. On each falling edge of SCLK, the 12 bits consisting of SB = 1, OP = 1,
and the10-bit address are written to the serial input shift register of the M21131/M21151. On the first rising edge
following the address LSB, the SB and eight bits of the data are shifted out on SDO. The first bit output on SDO for
a read operation is always 0.
In a read cycle, all extra clock cycles will result in invalid data. For invalid SB/OP, the operation is undefined. The
falling edge of XCS always resets the serial operation for a new read/write cycle.
Table 4-3 contains the timing specifications for the serial programming interface.
211x1-DSH-001-I
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