AN3004 Datasheet, PDF (4/5 Pages) M/A-COM Technology Solutions, Inc. – Programming Guide, Integer N PLL Synthesizer 100 - 2800 MHz

Application Note
AN3004
Programming Guide, Integer N PLL Synthesizer
100 - 2800 MHz
The complete 21-bit binary frequency word to be
programmed would then be as below.
Function and Initialisation Latches
Both the 18-bit Function and Initialisation Latches
write to the same registers. For the Function Latch,
(C2, C1) = (1, 0).
MSB
Rev. V2
For the Initialisation Latch, (C2, C1) = (1, 1). Load-
ing the Function Latch with (C2, C1) = (1, 1) imme-
diately followed by an R Counter load, then an N
Counter load, efficiently programmes the control
register. Setting (C2, C1) = (1, 1) programmes the
same Function Latch as a load with (C2, C1) = (1,
0), and additionally provides an internal reset
pulse. This programme sequence ensures that the
counters are at load point when the N Counter data
is latched in and the part will begin counting in
close phase alignment.
LSB
X0
0
1
0
0
01
1 010 1 1 0 1 0
0
0
0
1
Programming the Function Latch
The serial data format is shown below, together with the programming table for the Function Latch.
MSB
LSB
F F F F F F F F FFFF F F F F F F F C C
18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 4 3 2 1 2 1
F18 F17-15 F14-11 F10
F9
F8 F7
Power
down
mode
Test
modes
Timeout
counter
value
Timeout
counter
enable
FastLock FastLock
control enable
CP tri-
state
Bit function description
F1: The counter reset bit, when activated, allows the
reset of both N and R Counters. In normal operation
this is set to 0.
F2, F18: The powerdown bits provide programmable
powerdown modes. In normal operation these are
both set to 0.
F3-5: These bits control the function of the Fo/LD out-
put of the PLL IC. On M/A-COM synthesizers, bits
(F5, F4, F3) should be set to (0, 0, 1) for digital lock
detect or (1, 0, 1) for analog open-drain lock detect.
In digital mode, the Lock Detect output (pin 9 of the
synthesizer) goes HIGH when the absolute phase
error is <15ns for 3 consecutive phase comparator
cycles if bit R19 is LOW, or 5 consecutive phase com-
parator cycles if bit R19 is HIGH. If the absolute
phase error >30ns for a single phase comparator cy-
cle, Lock Detect will go LOW.
F6
F5-3 F2
F1
C2
C1
PD Fo/LD Power Counter
polarity control down reset
1
0
In analog mode, when the loop is locked, Lock Detect
is HIGH with narrow LOW pulses at the phase com-
parison frequency. When the loop is out of lock, Lock
Detect alternates between HIGH and LOW, at a rate
dependent on the frequency error. An external filter is
needed, to turn these conditions into stable HIGH or
LOW states. See Application Note AN3003 for notes
on filter design.
F6: The phase detector polarity bit should be set to 1.
F7: The charge pump tri-state bit should be set to 0 for
normal operation.
F8: M/A-COM synthesizers are not designed to use Fast-
Lock modes, so F8 should be set to 0.
F9-14: The FastLock and timeout counter control bits
should be set to 0 on M/A-COM synthesizers.
F15-17: These are for test modes, and should be set to 0
for normal operation.
4
Visit www.macomtech.com for additional data sheets and product information.
M/A-COM Technology Solutions Inc. and its affiliates reserve the right to make
changes to the product(s) or information contained herein without notice.
For more detailed information on the operation of the
PLL IC, please refer to the National Semiconductor
LMX2326 data sheet.
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