28333-DSH-001-A Datasheet, PDF (36/65 Pages) M/A-COM Technology Solutions, Inc. – Single/Dual/Triple E3/DS3/STS-1

2.0 Functional Description
2.5 Additional CX2833i Functions
CX28331/CX28332/CX28333 (-1x)
Single/Dual/Triple E3/DS3/STS-1 Line Interface Unit
2.5 Additional CX2833i Functions
2.5.1 Bias Generator
To achieve good isolation between the channels, each channel utilizes an
independent power and ground to both transmit and receive. Additionally, each
channel has its own band gap voltage reference. Because only one external
resistor for current generation exists, only one band gap voltage can be used. The
band gap from Ch1 has been chosen for this task.
The 12.1 kΩ external resistor from pin RBIAS to ground, is specified to have
a tolerance of ±1%. This helps to keep tighter control on power dissipation and
circuit performance.
NOTE: Capacitance should be kept to a minimum on the RBIAS pin.
2.5.2 Power-On Reset (POR)
If the system cannot guarantee a valid REFCLK frequency input during the POR
cycle, the CX2833i devices require assertion (active-high input pulse width, 1 µs
minimum) of the external reset signal (RESET, Pin 78 [80-pin package], Pin 97
[100-pin package]). Valid operation frequencies are DS3 (44.768 MHz ±20
ppm), E3 (34.368 MHz ±20 ppm), and STS-1 (51.84 MHz ±20 ppm). Please
refer to the CX28331/2/3 Evaluation Module User Guide for crystal oscillator
specifications and vendor listings.
A POR circuit is provided in the CX2833i device to initialize all resettable
digital logic and analog control lines. The POR circuit uses a fixed RC timer
(~1µs) to deassert itself when the power supply voltage reaches a minimum level
(~2 V). When the minimum supply voltage is reached (see Table 2-6), the
REFCLK input is counted for 128 clocks before the internal reset is deasserted.
At this time, the receiver block attempts to frequency lock (±5% tolerance) onto a
valid incoming REFCLK input. After frequency lock is achieved, the receiver
attempts to phase lock onto the valid RLINE receive signal.
NOTE: If a valid REFCLK input is not present when POR releases the internal
reset, the receiver block may be unable to lock to the RLINE receive
signal. It is common for some crystal oscillator types oscillate at a lower
fundamental frequency if the crystal oscillator supply has not reached its
minimum operation voltage.
2.5.3 Loopback Multiplexers (MUXes)
Two loopback MUXes per channel in the CX2833i allow for local loopback
(terminal or framer side), remote loopback (cable side), or both. The RLOS signal
monitors the RX cable inputs irrespective of any loopback.
In remote loopback, set by asserting pin RLOOP high, the receive data
(retimed after clock recovery but not decoded) loops back into the pulse shaper in
place of the transmit data. Additionally, this data is sent out the RPOS, RNEG,
and RCLK pins.
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28333-DSH-001-A
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