XR1020-QH Datasheet, PDF (3/7 Pages) M/A-COM Technology Solutions, Inc. – Integrated LNA, Mixer and LO Buffer Amplifier

XR1020-QH
Receiver
31 - 36 GHz
Absolute Maximum Ratings^6,7,8
Parameter
Drain Voltage (V_D1,2,3)
Drain Current (I_D1,2,3)
Gate Voltage (V_G1,2,3)
Gate Voltage (V_G4)
RF Input Power
LO Input Power
Storage Temperature
Operating Temperature
Channel Temperature
Absolute Max.
+4.3 V
200 mA
-1.7 to 0 V
-4 V
5 dBm
13 dBm
-65°C to +150°C
-55°C to +85°C
+150ºC
6. Exceeding any one or combination of these limits may cause
permanent damage to this device.
7. MACOM does not recommend sustained operation near these
survivability limits.
8. Operating at nominal conditions with T_J ≤ +150°C will ensure
MTTF > 1 x 10⁶ hours.
Rev. V1
Handling Procedures
Please observe the following precautions to avoid
damage:
Static Sensitivity
These electronic devices are sensitive to
electrostatic discharge (ESD) and can be damaged
by static electricity. Proper ESD control techniques
should be used when handling these devices.
Recommended Board Layout^9,10
App Note [1] Biasing -
As shown in the Pin Configuration table, the
XR1020-QH is operated by biasing V_D1,2,3 at 3 V
with 10, 30, 65 mA respectively. Additionally, a fixed
voltage bias of -3 V is required for mixer bias. It is
recommended to use active bias on V_G1, V_G2, and
V_G3 to keep the currents in V_D1, V_D2, and V_D3
constant in order to maintain the best performance
over temperature. Depending on the supply voltage
available and the power dissipation constraints, the
bias circuit may be a single transistor or a low power
operational amplifier, with a low value resistor in
series with the drain supply used to sense the
current. The gate of the pHEMT is controlled to
maintain correct drain current and thus drain
voltage. The typical gate voltage needed to do this
is -0.4 V. Make sure to sequence the applied voltage
to ensure negative gate bias is available before
applying the positive drain supply.
App Note [2] Board Layout -
It is recommended to provide 100 pF decoupling
capacitors as close to the bias pins as possible (see
board layout), 10 μF capacitors can be added further
along the DC lines.
9. Recommended decoupling capacitors:
100 pF, 0402
10 µF, 0805 (optional)
10.Recommend to externally ground all N/C pins.
3
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