M02050 Datasheet, PDF (2/2 Pages) M/A-COM Technology Solutions, Inc. – Limiting Amplifier for Applications up to 2.5 Gbps

the input signal level is monitored by the level detector (which
also outputs the RSSI_PP voltage). As described in the RSSI_PP
section, this voltage is proportional to the input signal peak
to peak value. The voltage at ST_SET is internally compared to
the signal level from the level detector. When the level
detector voltage is less than V(ST_SET), LOS is asserted and
will stay asserted until the input signal level increases by a
predefined amount of hysteresis. When the input level
increases by more than this hysteresis above V(ST_SET), LOS is
de-asserted.
Peak-to-Peak Received Strength Indicator (RSSI_PP)
The RSSI_PP output voltage is logarithmically proportional to
the peak-to-peak level of the input signal. It is not necessary
to connect an external capacitor to this output. Internally, the
RSSI voltage is compared with a user selectable reference to
determine loss of signal as described in the previous section.
Jam Function
When asserted, the active high power down (Jam) pin forces
the outputs to a logic “one” state. This ensures that no data
is propagated through the system. The loss of signal detec-
tion circuit can be used to automatically force the data
outputs to a high state when the input signal falls below the
threshold. The function is normally used to allow data to
propagate only when the signal is above the user's bit-error-
rate requirement. It, therefore, inhibits the data outputs
toggling due to noise when there is no signal present
(“squelch”). In order to implement this function, LOS should be
connected to the Jam pin, thus forcing the data outputs to a
logic “one” state when the signal falls below the threshold.
Averaged Received Strength Indicator (RSSI_AVG)
The RSSI_AVG output current is a mirrored version of the
RxAVG_IN current from compatible TIAs. It sources rather than
sinks the current making it compatible with DDMI type inter-
faces.
RATE _SEL
REF
V_TT
Biasing
DINP
DINN
Limiting
Amplifier
Jam
Output
Buffer
PECLP
PECLN
RxAVG_IN
RSSI_AVG
Level
Shift
Offset Cancel
Level
Detector
Comparator
Threshold
Setting
Circuit
ST_SET
Vcc
M02050 Block Diagram
RSSI_PP
LOS
Product Highlights
Applications
• 2.5 Gbps STM-16/OC-48
SDH/SONET
• 1.06, 2.12 Gbps Fibre Channel
• 1.25 Gbps Ethernet
• 2.67 Gbps SDH/SONET with FEC
Features
• Operates with a 3.3V (“-14”) or
3.3V/5V (“-15”) supply
• 4 mV maximum input sensitivity at
2.5 Gbps
• CML outputs
• Rate selection for ≤ 1.25 Gbps
operation
• Average receive power monitor
output (RSSI_AVG)
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Ordering Information
• M02050-14 3.3V supply
• M02050-15 3.3V/5.5V supply