MRF175GU_17 Datasheet, PDF (15/17 Pages) M/A-COM Technology Solutions, Inc. – The RF MOSFET Line 200/150W, 500MHz, 28V

MRF175GU
The RF MOSFET Line
200/150W, 500MHz, 28V
Rev. V1
RF POWER MOSFET CONSIDERATIONS
MOSFET CAPACITANCES
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure de-
termines the capacitors from gate–to–drain (Cgd), and gate–
to–source (Cgs). The PN junction formed during the fabrica-
tion of the MOSFET results in a junction capacitance from
drain–to–source (Cds).
These capacitances are characterized as input (Ciss),
output (Coss) and reverse transfer (Crss) capacitances on
data sheets. The relationships between the inter–terminal
capacitances and those given on data sheets are shown
below. The Ciss can be specified in two ways:
1. Drain shorted to source and positive voltage at the
gate.
2. Positive voltage of the drain in respect to source
and zerovolts at the gate. In the latter case the
numbers are lower. However, neither method
represents the actual operating conditions in RF
applications.
The Ciss givenin the electrical characteristics table was
measured using method 2 above. It should be noted that-
Ciss, Coss, Crss are measured at zero drain current and are
provided for general information about the device. They are
not RF design parameters and no attempt should be made
to use them as such.
LINEARITY AND GAIN CHARACTERISTICS
In addition to the typical IMD and power gain, data pre-
sented in Figure 3 may give the designer additional infor-
mation on the capabilities of this device. The graph repre-
sents the small signal unity current gain frequency at a
given drain current level. This is equivalent to fT for bipolar
transistors. Since this test is performed at a fast sweep
speed, heating of the device does not occur. Thus, in nor-
mal use, the higher temperatures may degrade these char-
acteristics to some extent.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, VDS(on), occurs in the
linear region of the output characteristic and is specified un-
der specific test conditions for gate–source voltage and drain
current. For MOSFETs, VDS(on) has a positive temperature
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the MOSFET is a polysilicon material, and is
electrically isolated from the source by a layer of oxide. The
input resistance is very high — on the order of 109 ohms —
resulting in a leakage current of a few nanoamperes. Gate
control is achieved by applying a positive voltage slightly in
excess of the gate–to–source threshold voltage, VGS(th).
Gate Voltage Rating — Never exceed the gate voltage rat-
ing (or any of the maximum ratings on the front page). Ex-
ceeding the rated VGS can result in permanent damage to
the oxide layer in the gate region.
Gate Termination — The gates of this device are essen-
tially capacitors. Circuits that leave the gate open–circuited
or floating should be avoided. These conditions can result in
turn–on of the devices due to voltage build–up on the input
capacitor due to leakage currents or pickup.
Gate Protection — These devices do not have an internal
monolithic zener diode from gate–to–source. If gate protec-
tion is required, an external zener diode is recommended.
Using a resistor to keep the gate–to–source impedance low
also helps damp transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the
gate may be large enough to exceed the gate–threshold
voltage and turn the device on.
HANDLING CONSIDERATIONS
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding
straps and devices not in the antistatic packaging should be
kept in metal tote bins. MOSFETs should be handled by the
case and not by the leads, and when testing the device, all
leads should make good electrical contact before voltage is
applied. As a final note, when placing the FET into the sys-
tem it is designed for, soldering should be done with
grounded equipment.
DESIGN CONSIDERATIONS
The MRF175G is a RF power N–channel enhancement
mode field–effect transistor (FETs) designed for HF, VHF
andUHF power amplifier applications. M/A-COM RF MOS-
FETs feature a vertical structure with a planar design. M/A-
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