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M21528-13 Datasheet, PDF (15/22 Pages) M/A-COM Technology Solutions, Inc. – Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
M21528-13
Dual 3G/HD/SD-SDI Multi-rate Video Cable Driver
Rev V4
4.2
Input Description
The M21528 has differential inputs, with integrated 50 pull ups to AVDDI. AVDDI may be supplied from a 1.2V,
1.8V, 2.5V, or 3.3V supply. The input buffers are compatible with PCML, LVDS or LVPECL signal levels.
To improve signal integrity in large systems, all inputs have programmable input equalization (IE) with three gain
levels: 0 dB, 4 dB, 6 dB.
Setting the gain to 0dB effectively disables the IE feature. The pins EN_EQ0 and EN_EQ1 allow for the selecting
the proper level of input equalization based on the board characteristics for each input. The maximum level of
equalization compensates for up to 36” of FR4 trace. The operation of the EN_EQ0/1 pin is summarized in
Table 4-1 below.
Table 4-1.
Pin
EN_EQ0
EN_EQ1
Operation of EQ_EN0 and EQ_EN1 Pins
Level
Function
L
SDI0P/N IE EQ gain = 0 dB
F
SDI0P/N IE EQ gain = 4 dB
H
SDI0P/N IE EQ gain = 6 dB
L
SDI1P/N IE EQ gain = 0 dB
F
SDI1P/N IE EQ gain = 4 dB
H
SDI1P/N IE EQ gain = 6 dB
In 3G/HD/SD SDI applications, it is best to avoid AC coupling data interfaces between devices, if possible. DC
coupling will result in increased system jitter margin. Also, DC coupling eliminates the requirement for additional
components on the board. In order to accommodate DC coupling to the upstream device, the AVDDI domain of the
M21528 is electrically isolated from all other power domains on chip. This allows for it to be tied to the VDD of the
previous device’s driver enabling a fully DC coupled system, as shown below.
Upstream
VDD
50
1.2V – 3.3V
M21528
AVDDI
50
15
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