M21012 Datasheet, PDF (15/73 Pages) M/A-COM Technology Solutions, Inc. – Quad Multi-Rate CDR

Functional Description
Table 1-6. Hardwired Data-Rates and Associated Reference Clock Frequencies
Pins
MF [3:0]
Application
Signal Data-Rate (Mbps) Reference Frequency (MHz)
0000
0001
0010
0011
0101
0110
0111
1000
1001
1010
1011
1100
1101
10x Fibre Channel - XAUI
10 Gigabit Ethernet - XAUI
STS-48 + FEC
STS-48
2x Fibre Channel
Gigabit Ethernet
1x Fibre Channel
STS-12
STS-3
STS-1
ESCON
FE
STS-48
3187.5
3125
2666
2488.32
2125
1250
1062.5
622.08
155.52
51.84
200
125
2488.32
159.375
156.25
19.44
19.44
106.25
125
106.25
19.44
19.44
19.44
10
12.5
155.52
1.2.8
Two-Wire Serial Interface
The two-wire serial interface is compatible with the I²C standard. The M21012 supports the read/write slave-only
mode, 7-bit device address field width, and supports the standard rate of 100 Kbps, fast mode of 400 Kbps, and
high-speed mode of 3.4 Mbps. The 7-bit address for the device is determined with MF [6:0], which allows for a max-
imum of 124 unique addresses for this device. The four addresses 00001xx (4, 5, 6, 7) are reserved and should not
be used. SDA (MF11) and SCL (MF10) can drive a maximum of 500 pF each at the maximum rate. During the
write mode from the master to the M21012, data is latched into the internal M21012 registers on the rising edge of
SCL, during the acknowledge phase (ACK) of communication. Table 1-7 summarizes the multifunction pins for the
two-wire serial interface mode. For further information on timing, please see the I ²C bus specification standard.
Table 1-7.
Pin
MF0
MF1
MF2
MF3
MF4
MF5
MF6
MF10
MF11
Multifunction Pins for Two-Wire Interface
Function
Description
Address bit 0
Address bit 1
Address bit 2
Address bit 3
Address bit 4
Address bit 5
Address bit 6
SCL
SDA
7-bit device address; address bit 0 is LSB, address bit 6 is MSB
Clock input
Data input/output (open drain)
210xx-DSH-001-D
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