M539 Datasheet, PDF (1/3 Pages) M/A-COM Technology Solutions, Inc. – Drivers for GaAs FET MMIC Switches and Digital Attenuators

Application Note
M539
Drivers for GaAs FET MMIC Switches and Digital Attenuators
Rev. V3
Application Note
M/A-COM’s Microelectronics Division produces a
silicon CMOS Application Specific Integrated Cir-
cuit (ASIC) that drives GaAs Field Effect Transistor
(FET) based switches or digital attenuators from a
single TTL or compatible IC. These ASICs are
available in single (SW-109) or squad-channel
(SWD-119) plastic packages. This application note
provides technical and application information to
simplify the use of these drivers.
Design Considerations
To accommodate the need for a large output volt-
age swing and low DC power dissipation, the ASIC
design uses a standard CMOS analog fabrication
process. A buffering stage is added so that the
driver will switch with standard TTL, as well as
CMOS logic levels, increasing the flexibility and
ease of use for system designers. The ASIC driver
requires only a single control input per channel,
further simplifying the external drive requirements.
Introduction
GaAs MMIC control devices like switches and digi-
tal attenuators typically employ FET technology.
The most common FET is the N-channel depletion
mode device which has low source-to-drain resis-
tance when there is no bias. When a negative volt-
age is applied to the gate, the electric field narrows
the channel, increasing the source-to-drain resis-
tance. The voltage that closes off the channel and
created the highest resistance of the FET is known
as the “pinch-off” voltage. For M/A-COM FETs, the
pinch-off voltage is typically -2.5 volts.
FETs can be arranged in series and/or shunt con-
figurations, then biased to provide varying insertion
loss values. By varying the gate voltage between
zero volts and some value greater than pinch-off
(typically -5 to -8 volts), the FET acts as a voltage
variable resistor. If the device is biased at the ex-
tremes (0 V and -5 V), on and off switching results,
providing the basis for both the GaAs MMIC
switches and digital attenuators. Switches require
low loss (on) and high loss (off) paths during opera-
tion. Digital attenuators use bits of different loss
values to switch in or out of the transmission path,
either individually or in combination.
FET based control devices are most often config-
ured in series/shunt arrangements, resulting in the
broadest bandwidth for the available size. In these
configurations, the driver output must be comple-
mentary, supplying different voltage levels to the
series and shunt mounted FETs. This is usually
accomplished with level translation and multiple IC
chips, increasing the complexity, size, and DC
power dissipation of the device.
TTL Input Buffer
The input buffer operates at standard TTL input
levels, despite being fabricated with a CMOS proc-
ess. The CMOS process keeps the quiescent cur-
rent in the microamp range when the input control
signal is close to V_CC. When the control signal
level drops, the quiescent current increases. At a
control voltage of 2.9 volts, the current increases to
only 0.7 mA.
As the block diagram shows, the TTL input buffer-
ing is followed by additional buffering stages that
take the input TTL signal and generate two comple-
mentary signals. The two signals, noninverting and
inverting, are also buffered to ensure they are at
the proper levels. The need for complementary
signals arises, as described earlier, from the se-
ries-shunt schematic of most GaAs MMIC based
control devices.
Voltage Translator
The input buffering is followed by a voltage transla-
tor. This stage translates the 0-V and 5-V TTL lev-
els to the voltage levels required to switch the
GaAs MMIC device to the on and off states. As
described earlier, switching in a GaAs FET MMIC
occurs when the incident voltages change from 0 V
to a level greater than pinch-off. These drivers in-
clude a feature in the translator section that allows
the user to optimize the performance of the GaAs
MMIC device being driven.
At pinch-off, the electric field on the gate closes the
channel of the FET resulting in the high resistance
state of the FET. If the gate voltage is near the
pinch-off value, the incident RF voltage may modu-
late this resistance.
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