AN3010 Datasheet, PDF (1/3 Pages) M/A-COM Technology Solutions, Inc. – An Examination of Recovery Time of an Integrated Limiter/LNA

An Examination of Recovery Time of an Integrated Limiter/LNA
■ Jim Looney, David Conway, and Inder Bahl
GaAs monolithic microwave integrated circuits
(MMICs) are widely used in commercial and mili-
tary microwave systems. Due to the fine geometry
used in MMIC transistors, these circuits are susceptible to
damage from high-power spurious electromagnetic (EM)
radiation, either from microwave transmitters or nuclear
electromagnetic pulse. Especially, low noise amplifiers
(LNAs) in the front-end of microwave systems need high
power protection because these amplifiers can sustain only
low input power levels in the range of 10–20 dBm continuous
wave (CW). To protect these circuits and maintain low noise
figure, a high power and low loss limiter is required.
The purpose of this application note is to document the test
methodology employed and test results achieved measuring
the small-signal gain recovery time of a balanced LNA with an
integrated Schottky diode limiter and high power load.
Device Under Test
The circuit selected for this investigation was the commercial-
ly available M/A-COM limiter/LNA MMIC [1]. This
limiter/LNA has an operating bandwidth of 8.5 to 12 GHz, a
nominal gain of 16 dB, a noise figure (NF) < 3 dB, and an
input third-order intercept (TOI) of 13 dBm. Operating bias
voltages and currents are 5 V, 130 mA nominal, –5 V, 4 mA
nominal for the drain and gate, respectively. The active device
employed in this IC is the low noise multifunction self-
aligned (MSAG) metal-semiconductor field-effect transistor
(MESFET). Salient features of this circuit are:
• single chip, no extra components and assembly, low cost
solution
• balanced configuration, built-in couplers
• high-power termination resistor on the chip
• limiter parasitic capacitance part of the LNA’s input
match, improved noise figure with respect to discrete
solutions
• high-output, third-order intercept point
• uses standard, reliable and high performance MSAG
MESFET technology.
A block diagram of the high power limiter/LNA MMIC is
shown in Figure 1. Figure 2 shows the photograph of the two-
stage balanced limiter/LNA. The chip measures 4.6 ×3.1 mm.
The design of integrated high power limiter/LNA has been
described in [2].
Test Methodology
The limiter recovery time was measured by pulsing the input
RF signal from a small signal level to a high power state
Lange
Coupler
Limiter
LNA
In
50-Ω
High
Power
Single-Ended
Amplifier
Lange
Coupler ^{50 Ω}
Out
Jim Looney, David Conway, and Inder Bahl ([e-mail])
are with M/A-COM, Inc., 5310 Valley Park Drive,
Roanoke, VA 24019. USA
Figure 1. A balanced three-stage LNA with limiter.
March 2004
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