AN3003 Datasheet, PDF (1/3 Pages) M/A-COM Technology Solutions, Inc. – Integrating SMT Synthesizer Solutions into Wireless Designs

Application Note
AN3003
Integrating SMT Synthesizer Solutions into Wireless Designs
Rev. V2
Introduction
Today’s high performance, low-cost, SMT solutions
for frequency generation greatly simplify the
designer’s task in developing wireless products.
Properly interfacing these devices into the circuit is
however essential to achieving maximum
performance. This application note highlights some
primary areas of concern, some analysis
methodologies and suggests possible solutions.
To prevent noise from the digital circuitry in the
synthesizer from adversely affecting the VCO, the
PLL and VCO supply rails must be adequately de-
coupled and filtered from each other. In order to fa-
cilitate this, M/A-COM synthesizers typically utilize
separate VCO and PLL supply pins on the package.
A suitable circuit is shown in Figure 1. Component
values should be selected that will optimize attenua-
tion of the PLL operating frequency. (step size).
Power Supplies
Clean sources of regulated DC power are essential
in minimizing spurious signals from synthesizers.
You can calculate the quality of the supply
necessary by the following formula:
+Vcc
PLL
VCO
Volts (rms) ≤ ^{2 (Fs) (10) dBc/20}
Pushing Figure
Where:
Fs = Spur Frequency
dBc = Desired Spur specification in dBc
Pushing Figure = Pushing Figure in Hz/Volt
For example, with a spur frequency of 1 kHz, a spur
specification of –80 dBc and a pushing figure of
3MHz/volt, the ripple voltage on the supply must be
no greater than 47nV rms. It is good design practice
to allow for a margin in the spur specification. For
this example, we use –70dBc plus a 10 dB margin
for -80 dBc.
Utilizing low-noise regulator designs is critical in
achieving the phase noise specifications of these
devices. Many DC regulators have their noise
output specified in a bandwidth. For example, the
LT1761 is specified as 20 V rms typical in 10Hz to
100kHz. Using the previous formula, the maximum
allowable noise voltage density at a given offset can
be estimated.
Noise Voltage Density ≤
2 (Fs) (10) ^(dBc/Hz)/20
Volts
(Hz)
Pushing Figure
Relating the noise density to a regulator
manufacturer’s specification is difficult unless the
amplitude/frequency distribution is known. A first
order assessment can be made, however if the
distribution is assumed flat.
Figure 1
Note: Some synthesizers, such as the
MASYVS0060-XXXX series, have a single supply
pin, and incorporate an on-board regulator and de-
coupling between the VCO and PLL. This greatly
reduces their sensitivity to power supply noise and
ripple.
Synthesizers must be mounted directly on a ground
plane and all DC ground returns should be brought
to it.
Output Load
It is imperative that the designer understands the
load that will be presented to the device. M/A-COM
synthesizers are designed for 50 ohm nominal out-
put impedance. Severe mismatches can increase
the VCO’s phase noise or pull a VCO to the point
where it will not oscillate into that load. When it is
known that the VSWR of the load will be poor i.e.
>2.0:1 any phase angle, a buffered output synthe-
sizer should be specified. Alternatively, the designer
can provide the buffer. The best form of load con-
sists of a resistive pad followed by an amplification
stage to restore the output power. A representative
circuit is shown in Figure 2.
1
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