28326-BRF-001-A_15 Datasheet, PDF (1/2 Pages) M/A-COM Technology Solutions, Inc. – Digital Jitter-Attenuator

Highly-Integrated, Fully-Featured 6-port DS3/E3/STS-1
Jitter-Attenuator and STS-1 to DS3/E3 Desynchronizer
M 2 8 3 2 6 Digital Jitter-Attenuator (DJAT)
Mindspeed Technologies™ offers its first
6-port DS3/E3/STS-1 Jitter-Attenuator and
desynchronizer based on DJAT technology
Mindspeed’s DJAT technology performs critical jitter-
attenuation and signal desynchronization functions to
improve performance and reliability in both telecommun-
ciations and data communications equipment surrounding
the edge of the optical network.
This high density, low power solution is designed for
transmission applications including add/drop multiplexers,
routers, ATM multi-service switches, digital cross connects,
and DS3 to STS-1 mappers. The M28326 6-port DJAT
device can be combined with Line Interface Units (LIUs)
and mapper devices in addressing traffic-aggregation
equipment needs in converting high-speed Synchronous
Transport Signal-1 (STS-1) streams to asynchronous
lower-speed DS3/E3 data rates for systems used in data
centers and points of presence (POPs).
The 12-port M28326 DJAT leverages Mindspeed’s advance
digital signal processing techniques along, with extensive
knowledge of analog mixed signal design, that provide the
first solution of its kind to adapt and fully smooth a STS-1
clock (with overhead gaps) to a network compliant DS3 or
E3 line clock.
The M28326 6-port DJAT complies with Telcordia GR-253
and GR-499, ETSI TBR-24, ANSI T1.105.03b, as well as ITU
G.751, G.755, G.783, and G.823 standards. For Category I
interfaces, the M28320 12-port DJAT device smooths the
inherent jitter due to demapping, bit stuffing and pointer
adjustments in DS3 or E3 payloads extracted from STS-1
> KEY FEATURES
> High density: up to 12 inde-
> One second timer for event
pendent jitter-attenuators and latching
desynchronizers for DS3/E3,
and STS-1 in one package
> Ability to dejitter AMI or
NRZ input data
> Low power: <250 mW maximum
power consumption
> Ability to independently bypass
the JAT for each channel
> Programmable FIFO depth
optimal for SONET/SDH
> Power-down control for each
channel
> Crystal-less jitter-attenuation _{> Small 15 mm BGA package}
> Programmable clocking of both
inputs and outputs on either edge
> Single 3.3 V supply
> Two PRBS generator/detector
per channel
frames, generating a network compliant clock. The M28326
6-port DJAT seamlessly interfaces with Mindspeed’s
DS3/E3/STS-1 LIU devices — M28331/2/3 (1/2/3-port),
M28335 (12-port), and CX28365 (12-port DS3/E3 framer
with ATM TC) — providing a complete solution for high
density DS3/E3 line cards.
Jitter Definition
Jitter is defined as the short-term variations of the
significant instants of any signal from their ideal position
in time. The short-term variations are phase oscillations
of the digital signal. Clock jitter can lead to incorrect
data bit sampling, resulting in bit errors.
Jitter can be caused by any or all of the following:
– Interference
– Stuffing jitter
– Oscillator phase noise – Demapping jitter
– Signal distortion
– Pointer jitter
>