LY6210248 Datasheet, PDF (9/13 Pages) Lyontek Inc. – 1024K X 8 BIT LOW POWER CMOS SRAM

®
Rev. 0.4
LY6210248
1024K X 8 BIT LOW POWER CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC_* = Read Cycle Time
SYMBOL TEST CONDITION
MIN.
VDR CE# ≧ VCC - 0.2V or CE2 ≦0.2V
1.5
VCC = 1.5V
-LL -
IDR CE# ≧VCC - 0.2V or CE2 ≦0.2V -LLE -
Other pins at 0.2V or VCC - 0.2V _{-LLI -}
tCDR
See Data Retention
Waveforms (below)
0
tR
tRC_*
TYP.
-
5
5
5
-
-
MAX.
5.5
30
40
50
UNIT
V
µA
µA
µA
-
ns
-
ns
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (CE# controlled)
Vcc
CE#
Vcc(min.)
tCDR
VIH
VDR ≧ 1.5V
CE# ≧ Vcc-0.2V
Vcc(min.)
tR
VIH
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Vcc
CE2
Vcc(min.)
tCDR
VIL
VDR ≧ 1.5V
CE2 ≦ 0.2V
Vcc(min.)
tR
VIL
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
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