LY65W1024_12 Datasheet, PDF (7/13 Pages) Lyontek Inc. – 128K X 8 BIT HIGH SPEED CMOS SRAM

®
Rev. 1.1
LY65W1024
128K X 8 BIT HIGH SPEED CMOS SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
Address
CE#
CE2
WE#
Dout
Din
tWC
tAW
tCW
tAS
tWP
tWHZ
(4)
tWR
TOW
High-Z
(4)
tDW
tDH
Data Valid
WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6)
Address
CE#
CE2
tWC
tAW
tAS
tCW
WE#
Dout
tWP
tWHZ
(4)
Din
tWR
High-Z
tDW
tDH
Data Valid
Notes :
1.WE#, CE# must be high or CE2 must be low during all address transitions.
2.A write occurs during the overlap of a low CE#, high CE2, low WE#.
3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the
bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance
state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
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