LY61L51216A_13 Datasheet, PDF (1/12 Pages) Lyontek Inc. – 512K X 16 BIT HIGH SPEED CMOS SRAM

®
Rev. 1.3
LY61L51216A
512K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Description
Initial Issued
“CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2” for TEST
CONDITION of Average Operating Power supply Current
Icc1 on page3
2.Revised ORDERING INFORMATION Page13
1.Revise “TEST CONDITION” for VOH, VOL on page 4
IOH = -8mA revised as -4mA
IOL =4mA revised as 8mA
2. Revise VIH(max) & VIL(min) note on page 4
VIH(max) = VCC + 2.0V for pulse width less than 6ns.
VIL(min) = VSS - 2.0V for pulse width less than 6ns.
Revised the address pin sequence of TSOP-II pin configuration on
page 2 in order to be compatible with industry convention. (No
function specifications and applications have been changed and all
the characteristics are kept all the same as Rev 1.2 )
Issue Date
2012/2/22
July.19. 2012
June. 04. 2013
Oct. 30. 2013
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, lndustry E . Rd. 9, Science-Based Industrial Park, Hsinchu 300, Taiwan
TEL: [phone]
FAX: [phone]
0