LY61L25616A_13 Datasheet, PDF (1/15 Pages) Lyontek Inc. – 256K X 16 BIT HIGH SPEED CMOS SRAM

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Rev. 1.4
LY61L25616A
256K X 16 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Description
Initial Issue
“CE# ≧VCC - 0.2V” revised as ”CE# ≦0.2V” for TEST CONDITION
of Average Operating Power supply Current
Icc1 on page3
Revised VIH(max)/VIL(min) in
DC ELECTRICAL CHARACTERISTICS
Added in tBA/tBHZ*/tBLZ*
in AC ELECTRICAL CHARACTERISTICS
Added WRITE CYCLE 3 in TIMING WAVEFORMS
1.Revise “TEST CONDITION” for VOH, VOL on page 5
IOH = -8mA revised as -4mA
IOL =4mA revised as 8mA
2. Revise VIH(max) & VIL(min) note on page 5
VIH(max) = VCC + 2.0V for pulse width less than 6ns.
VIL(min) = VSS - 2.0V for pulse width less than 6ns.
Revised the address pin sequence of TSOP-II pin configuration on
page 3 in order to be compatible with industry convention. (No
function specifications and applications have been changed and all
the characteristics are kept all the same as Rev 1.3 )
Added tBW in AC ELECTRICAL CHARACTERISTICS
Revised WRITE CYCLE 1,2 in TIMING WAVEFORMS
Issue Date
Jul.12.2012
Jul.19.2012
May.7.2013
Jun.04.2013
Sep.23.2013
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: [phone]
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