LXT305A Datasheet, PDF (7/18 Pages) Level One – Integrated T1/E1 Short-Haul Transceiver wtih Transmit JA

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To allow a host microprocessor to access and control the
LXT305A through the serial interface, MODE is set High.
The serial interface (SDI/SDO) uses a 16-bit word consist-
ing of an 8-bit Command/Address byte and an 8-bit Data
byte. Figure 3 shows the serial interface data structure and
relative timing.
The Host Mode provides a latched Interrupt output (INT)
which is triggered by a change in the Loss of Signal (LOS)
and/or Driver Performance Monitor (DPM) bits. The Inter-
rupt is cleared when the interrupt condition no longer
exists, and the host processor enables the respective bit in
the serial input data byte. Host Mode also allows control of
the serial data and receive data output timing. The Clock
Edge (CLKE) signal determines when these outputs are
valid, relative to the Serial Clock (SCLK) or RCLK as
listed in Table 3.
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CS
SCLK
ADDRESS / COMMAND BYTE
DATA INPUT / OUTPUT BYTE
R/W A0
A1
A2 A3
A4
A5
A6 D0
D1
D2
D3
D4 D5
D6
D7
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ADDRESS /
COMMAND
R/W
0
A0
0
0
0
1
0
A4
X
R/W- = 1: Read
A6
R/W- = 0: Write
BYTE
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CLEAR INTERRUPTS
X=DON’T CARE
SET LOOPBACKS OR RESET
INPUT
DATA
BYTE
LOS
D0 (LSB)
DFM
EC1
EC2
EC3
REMOTE LOCAL
TAOS
D7(MSB)
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