LXT310 Datasheet, PDF (12/18 Pages) Level One – T1 CSU/ISDN PRI Transceiver

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Figure 7 is a typical 1.544 Mbps ISDN PRI application
with the LXT310, a T1/ESF framer and an LXP600A clock
adapter. The LXT310 is operating in the Hardware Mode
with B8ZS encoding enabled (MODE pin 5 tied to RCLK).
As in the T1/CSU application, Figure 6, this configuration
is illustrated with a single power supply bus. CMOS con-
trol logic is used to set both LBO pins high, selecting the
22.5 dB LBO, and the EGL pin is tied low, allowing for full
receiver gain. The TAOS, LLOOP and RLOOP diagnostic
modes are individually controllable. The RCLK input to
the OR gate at RLOOP allows for clocking of the RLOOP
pin, which enables network loopback detection. The
receive and transmit line interfaces are identical to the Host
Mode application shown in Figure 6.
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