LF4460 Datasheet, PDF (18/32 Pages) LUXPIA – Video Memory / FIFO

Register 0, 1
2-D Data
Row Length
Configuration Register Definitions
PRELIMINARY
LF4460
LF4430
LF4415
Video Memory / FIFO
FRAME
MEMORY
Register 0,1 = ROW_LENGTH[11:0] - for 2-D Cartesian address mapping
The memory can be addressed using the external 24bit address port either as a 2-Dimensional
Cartesian address (in terms of row/column coordinates) or simple linear address (such as 0 to FFFFFF).
As a 2-D address, the lower 12bits of ADDR port defines the X/Column component and the upper
12bits define the Y/Row component See table below. If 2-D addressing is desired** and the line/row
length of the data array is ‘N’, ROW_LENGTH[11:0] must be loaded as ‘N’. When linear addressing
is required, the ADDR port acts as a 24bit linear address. Setting ROW_LENGTH to 0 causes the
incoming address to be interpreted simply as a linear address (or equivalently, a Cartesian address
with 4095 pixels per line).
Register 0 = ROW_LENGTH[11:8] (DEFAULT= 0000)
3:0 = ROW_LENGTH[11:8] Most significant 4 bits of the 12bit ROW_LENGTH
Register 1 = ROW_LENGTH[7:0] (DEFAULT= 00000000)
7:0 = ROW_LENGTH[7:0]
Least significant 8 bits of the 12bit ROW_LENGTH
Register 2 - 8
24bit External Address Mapping
ADDR[23:12]
ADDR[11:0]
2-D Addresses (non-zero row_length) Y / Column Address X / Row Address
24bit Linear Address (row_length of 0)
ADDR[23:0]
**Application Example) An application requires the LF4430 to store a full frame of standard def D1 video
and requires 2-D address mapping (accessing memory locations based on a row/column address defined
by the 24bit external address port). The video in this example has 1716 samples per line. ROW_LENGTH
should be set to 1716 decimal = 6B4 hex. In order to address Line 255 and Column 511 of the frame,
Q1 = 0FF and D1 = 1FF.
Registers 2, 3, 4, 5, 6, 7, 8 = RESERVED
LOGIC Devices Incorporated
www.logicdevices.com
18
High Performance Memory Product
January 23, 2008 LDS-44xx-A