RDD106 Datasheet, PDF (2/2 Pages) LSI Computer Systems – SELECTABLE 6 DECADE CMOS DIVIDER

DYNAMIC ELECTRICAL CHARACTERISTICS:
(CL = 50 pF, TA = 25°C)
VDD MIN MAX
Clock Input Frequency
3.0V 0
5
4.5V 0
10
10V 0
20
15V 0
30
UNIT
MHz
MHz
MHz
MHz
Clock Output Propagation Delay,
CL = 15pF
4.5V -
10V -
30 ns
15 ns
Output Rise & Fall Times
4.5V -
10V -
40 ns
20 ns
Propagation Delay to Output
(per decade)
4.5V -
10V -
160 ns
75 ns
Reset Pulse Width
4.5V 160
10V 75
- ns
- ns
Reset Removal Time
4.5V -
10V -
160 ns
75 ns
Reset Propagation Delay
to Output
4.5V -
10V -
200 ns
100 ns
Select Input Setup Time
4.5V -
10V -
100 ns
50 ns
Dynamic VDD Current
Freq
5MHz 3.0V -
10MHz 4.5V -
20MHz 10V -
30MHz 15V -
0.3 mA
1.0 mA
6.5 mA
17 mA
Pin 5
10pF
10M
Pin 6
10pF
FIGURE 2
TYPICAL OSCILLATOR CIRCUIT - 10MHz TO 30MHz
Pin 5
22pF
10M
40pF
22k
Pin 6
FIGURE 3
TYPICAL OSCILLATOR CIRCUIT WITH TRIM - 2MHz AND BELOW
Pin 5
22pF
10M
40pF
22pF
Pin 6
FIGURE 4
TYPICAL OSCILLATOR CIRCUIT WITH TRIM - 2MHz TO 10MHz
CLOCK
INPUT
SIGNAL
R1
5
V DD
V DD
VSS
V SS
FIGURE 5. TYPICAL INPUT
If input signals are less than VSS or greater than VDD,
a series input resistor, R1, should be used to limit the
maximum input current to 2mA.
CLOCK IN
5
OSCILLATOR
EXTERNAL
COMPONENTS
FIGURE 6
RDD 106 BLOCK DIAGRAM
+V
8 V DD
-V
3 V SS
R
CLOCK
GENERATOR
÷10
÷10
÷10
÷10
÷10
÷10
CLOCK OUT
6
RESET 4
DIVIDER SELECT-1 ¹
DIVIDER SELECT-2 ₂
DECODER
RDD106-081007-2
1 OUT OF 6 SELECTOR
BUFFER
7 OUTPUT