ZSP540 Datasheet, PDF (1/2 Pages) LSI Computer Systems – Highly Efficient Quad-MAC DSP Core

ZSP540 - Highly Efficient
Quad-MAC DSP Core
O V E RV I E W
The ZSP540 processor core is a high-performance/power-efficient Quad-
MAC/Six-ALU implementation of the ZSP^® G2 architecture. The ZSP540 utilizes a
16-bit architecture with extensive 32-bit capabilities and sets an unmatched
balance of performance/power/size and memory utilization efficiency. The
Z.Turbo feature provides the SOC designer with the option to extend the ZSP540
Instruction Set and the ability to add application-specific acceleration logic.
TARGET MARKETS
• 2.5/3G wireless baseband processing
• Multimedia wireless and mobile devices
• Cable/xDSL
• Wireless LAN (WLAN)
• Set-top box and home gateways
• Multi-channel Voice Over IP (VoIP)
• Software Defined Radio (SDR)
A P P L I C AT I O N B E N E F I T S
• High-performance DSP capabilities
• Excellent power/cost/speed balance
• Excellent multimedia audio/video processing
• Power efficient baseband processing performance
• DSP and system control functions handling capabilities
128-bit
64-bit
64-bit
Prefetch Unit (PFU)
Instruction Cache
Load/Store Unit (LSU)
Dual AGU
Instruction
Sequence Unit
(ISU)
Register File
Pipeline
Control Unit
(PCU)
Interrupt Control
Co-Processor IF
Debug IF
Bypass Logic
File
Timers
Multiply/ALU Unit 0
40-bit 16x16 16x16
ALU MAC MAC
Multiply/ALU Unit 1
40-bit 16x16 16x16
ALU MAC MAC
ALU Unit
16-bit 16-bit
ALU ALU
C O R E F E AT U R E S
• Quad-MAC/Six-ALU DSP core
• 4+1 instructions per cycle
• Up to 350MHz, 8-stage pipeline design
• Up to 1750 million instructions/sec
• Dual 64-bit wide Load/Store data ports
• Z.Turbo coprocessor extensions capable
• 24-bit address space
• HW managed instructions scheduling
• HW/SW controlled power management
• Real-time trace and profiling capability
• Full AMBA/AHB support (optional)
• JTAG debug interface
• Static, single phase clocked design
• Compatible with all other ZSP cores
A R C H I T E C T U R E F E AT U R E S
• Embedded control processing efficiency
• 32-bit addressing capabilities
• 16 and 32-bit standard instruction set
• Extensive 32-bit and 40-bit support
• Easy to program instruction set
• Load/store register based instructions
• Outstanding code density
• User extensible instruction set
S U P P O RT
• Highly optimized C-compiler
• Multimedia, voice and wireless experts
• Local support by ZSP solution experts