LS7766 Datasheet, PDF (1/14 Pages) LSI Computer Systems – 32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER

LSI/CSI
LS7766
U_{® L}
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]
A3800
October 2007
32-BIT SINGLE- AXIS/DUAL-AXIS QUADRATURE COUNTER
FEATURES:
• Direct interface with Incremental Encoders
• Read/write registers for count and I/O modes. Count modes
include: non-quadrature (Up/Down), quadrature (x1, x2, x4.)
free-run, non-recycle, modulo-n and range limit
• Programmable IOs for Index and Marker Flags
• Separate mode-control registers for each axis
• 40MHz count frequency at 5V; 20MHz count frequency at 3V
• Sets of 32-bit counters, input registers, output registers,
comparators and octal Status registers for each axis
• Digital filtering of the input quadrature clocks
for noise immumity.
• Pin selectable 3-state Hex / Octal bus
• 3V to 5.5V operating voltage range
• Available in four different configurations identified
by the following suffixes:
DH = Dual-axis with pin selectable Hex/Octal IO Bus
DO = Dual-axis Octal IO Bus
SH = Single-axis pin selectable Hex/Octal IO Bus
SO = Single axis Octal IO Bus
LS7766DH-TS; LS7766DO, LS7766DO-S, LS7766DO-TS;
LS7766SO, LS7766SO-S, LS7766SO-TS; LS7766SH-TS
P/N = DIP; P/N-S = SOIC; P/N-TS = TSSOP
GENERAL DESCRIPTION:
The LS7766 consists of two identical modules of 32-bit programmable
up/down counters (CNTR) with direct interface to incremental encod-
ers. The modules can be configured to operate as quadrature-clock
counters or non-quadrature up/down counters. In both quadrature and
non-quadrature modes, the modules can be further configured into
free-running, non-recycle, modulo-n and range-limit count modes. The
mode configuration is made via two octal read/write addressable
mode control registers, MCR0 and MCR1. Data can be written into a
32-bit input data register (IDR), organized in addressable Word seg-
ments using the hex IO bus or in byte segments using the octal IO
Bus. The IDR can be used to store target encoder positions and com-
pared with the CNTR for generating marker flags when the CNTR
reaches the target value. A 32-bit digital comparator is included for
monitoring the equality of the CNTR to the IDR. Snapshots of the
CNTR value can be stored in a read-addressable 32-bit output data
register (ODR). The ODR can be read in Word segments or byte seg-
ments in accordance with the selected bus width. Data transfers
among the registers and various register reset functions are per-
formed by means of a write-addressable octal transfer control register
(TCR). A read-addressable octal status register (STR), stores the
count related status information such as CNTR overflow, underflow,
count direction, etc.
RS2 ₁
RS1 2
RS0 ₃
NC ⁴
DB0 5
DB1 ₆
DB2 7
DB3 8
DB4 ₉
DB5 ₁₀
DB6 11
DB7 12
DB8 ₁₃
DB9 ₁₄
DB10 ₁₅
DB11 16
DB12 ¹⁷
DB13 ₁₈
DB14 ¹⁹
DB15 ₂₀
NC ₂₁
NC 22
NC 23
V SS 24
48 V DD
47 PCKO
46 PCKI
45 RD/
44 WR/
43 CS/
42 NC
41 ^x1B
40 ^x1A
39 ^x1INDX/
38 ^x1FLGa
37 _x1FLGb
36 x1CKO
35 V SS
34 _IO16/
33 x0/_x1
32 _x0CKO
31 x0FLGb
30 x0FLGa
29 ^NC
28 ^x0INDX/
27 ^x0A
26 ^x0B
25 NC
Pin Assignment - Top View
7766-102307-1