LS7566R_08 Datasheet, PDF (1/18 Pages) LSI Computer Systems – 24-BIT x 4-AXES QUADRATURE COUNTER

LSI/CSI
LS7566R
U_{® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]}
A3800
24-BIT x 4-AXES QUADRATURE COUNTER
July 2008
FEATURES:
• Read/write registers for count and I/O modes.
Count modes include: non-quadrature (Up/Down), Quadrature
(x1, x2, x4), Free-run, Non-recycle, Modulo-n and Range limit
• Separate mode-control registers for each axis
• Interrupt output and interrupt mask register
• 40 MHz count frequency, 5V
20 MHz count frequency, 3V
• Sets of 24-bit counters, preset registers, comparators and
output latches and 8-bit status registers for each axis
• Digital filtering of the input quadrature clocks for
noise immumity.
• 3-state Octal I/O bus
• 3V to 5.5V operating voltage range
• LS7566R-TS (TSSOP) - See Figure 1 -
GENERAL DESCRIPTION:
The LS7566R consists of four identical modules of 24-bit pro-
grammable counters with direct interface to incremental encod-
ers. The modules can be configured to operate as quadrature-
clock counters or non-quadrature up/down counters. In both
quadrature and non-quadrature modes, the modules can be fur-
ther configured into free-running, non-recycle, modulo-n and
range-limit count modes. The mode configuration is made
through two 8-bit read/write addressable control registers, MDR0
and MDR1. Data can be ported to a 24-bit preset register PR, or-
ganized in directly addressable (write-only) byte0 [PR0], byte1
[PR1] and byte2 [PR2] segments. PR can be transferred to the
24-bit counter CNTR, either by instruction to CMR or by hard-
ware input control. A 24-bit digital comparator perpetually checks
for the equality of the CNTR and the PR and can be used to set
an output flag when the equality occurs. For reading the CNTR,
its instantaneous value can be transferred to a 24-bit output latch
OL, either by instruction to CMR or by hardware input control.
The OL in turn can be read in directly addressable (read-only)
byte0 [OL0], byte1 [OL1] and byte2 [OL2] segments. An address-
able (read-only) Octal status register STR, stores the count re-
lated status information such as CNTR overflow, underflow,
count direction, etc. Data communication for read/write is per-
formed through an Octal 3-state parallel I/O bus.
REGISTER DESCRIPTION:
Following is a list of the hardware registers. There are four
sets of registers, with name prefixes x0 through x3 to refer
to axes x0 through x3.
7566R-072108-1
PIN ASSIGNMENT - Top View
RS2 1
RS1 2
RS0 3
CHS1 ₄
CHS0 5
NC 6
NC ₇
RD/ 8
CS/ 9
WR/ 10
DB0 ¹¹
DB1 ₁₂
DB2 13
DB3 14
DB4 15
DB5 ¹⁶
DB6 17
DB7 18
NC 19
NC ²⁰
PCK 21
GND 22
x0INDX/ ²³
x0A ²⁴
48 ^x0FLGa
47 x0FLGb
46 x1FLGa
45 INT/
44 NC
43 _GND
42 _x1FLGb
41 _x2FLGa
40 _x2FLGb
39 _x3FLGa
38 _x3FLGb
37 _VDD
36 _x3B
35 _x3A
34 _x3INDX/
33 _x2B
32 _x2A
31 _NC
30 _NC
29 x2INDX/
28 x1B
27 _x1A
26 x1INDX/
25 _x0B
FIGURE 1
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.