LS7215 Datasheet, PDF (1/8 Pages) LSI Computer Systems – PROGRAMMABLE DIGITAL DELAY TIMER

LSI/CSI
LS7215
LS7216
U_{® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]}
A3800
PROGRAMMABLE DIGITAL DELAY TIMER
July 2009
FEATURES:
• Programmable delay from microseconds to days
• Programmable delay controlled by 8 binary-weighted delay inputs
that can be latched from a shared 8-bit bus
• On chip oscillator (RC or Crystal) or external clock time base
• Selectable prescaler for real time delay generation based
on 50Hz/60Hz time base or 32,768Hz watch crystal
• Four operating modes
• Reset input for delay abort
• Low quiescent and operating current
• Direct relay drive
• +3V to +18V operation (VDD - VSS)
• LS7215, LS7216 (DIP); LS7215-S, LS7216-S (SOIC) - See Figure 1 -
DESCRIPTION:
The LS7215 and LS7216 are CMOS integrated circuits for gener-
ating digitally programmable delays. The delay is controlled by 8 bi-
nary weighted inputs, WB0 - WB7, in conjunction with an applied
clock or oscillator frequency. The programmed time delay man-
ifests itself in the Delay Output (OUT) as a function of the Oper-
ating Mode selected by the Mode Select inputs A and B: One-Shot,
Delayed Operate, Delayed Release or Dual Delay. The time de-
lay is initiated by a transition at the Trigger Input (TRIG).
I/O DESCRIPTION:
MODE SELECT Inputs A & B (Pins 1 & 2)
The 4 operating modes are selected by Inputs A and B
according to Table 1
TABLE 1. MODE SELECTION
A
B
MODE
0
0
One-Shot (OS)
0
1
Delayed Operate (DO)
1
0
Delayed Release (DR)
1
1
Dual Delay (DD)
PIN ASSIGNMENT - TOP VIEW
A1
B2
V DD (+V) ³
RC/CLOCK ₄
RCS/CLKS 5
PSCLS 6
RESET 7
V SS (-V) 8
OUT ⁹
OD OUT ₁₀
20 LOAD
19 TRIG
18 WB0
17 WB1
16 WB2
15 _WB3
14 WB4
13 ^WB5
12 _WB6
11 ^WB7
A1
B2
V DD (+V) ₃
XTLI/CLOCK ⁴
XTLO ⁵
PSCLS 6
RESET ₇
V SS (-V) 8
OUT 9
OD OUT ¹⁰
20 _LOAD
19 _TRIG
18 ^WB0
17 WB1
16 WB2
15 ^WB3
14 WB4
13 WB5
12 _WB6
11 WB7
Each input has an internal pull-up resistor of about 500kΩ.
One-Shot Mode (OS)
A positive transition at the TRIG input causes OUT to switch low
without delay and starts the delay timer. At the end of the pro-
grammed delay timeout, OUT switches high. If a delay timeout is in
progress when a positive transition occurs at the TRIG input, the
delay timer will be restarted. A negative transition at the TRIG input
has no effect.
Delayed Operate Mode (DO)
A positive transition at the TRIG input starts the delay timer. At the
end of the delay timeout, OUT switches low. A negative transition
at the TRIG input causes OUT to switch high without delay. OUT is
high when TRIG is low.
FIGURE 1
Delayed Release Mode (DR)
A negative transition at the TRIG input starts the delay timer.
At the end of the delay timeout, OUT switches high. A pos-
tive transition at the TRIG input causes OUT to switch low
without delay. OUT is low when TRIG is high.
Dual Delay Mode (DD)
A positive or negative transition at the TRIG input starts the
delay timer. At the end of the delay timeout, OUT switches to
the logic state which is the inverse of the TRIG input. If a de-
lay timeout is in progress when a transition occurs at the
TRIG input, the delay timer is restarted.
7215-072009-1