LS7183_09 Datasheet, PDF (1/4 Pages) LSI Computer Systems – QUADRATURE CLOCK CONVERTER

LSI/CSI
LS7183
LS7184
U_{® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]}
A3800
QUADRATURE CLOCK CONVERTER
January 2009
FEATURES:
PIN ASSIGNMENT - TOP VIEW
• x1, x2 and x4 resolution
• Programmable output pulse width (200ns to 140µs)
• Excellent regulation of output pulse width
RBIAS ¹
8 _UPCK
• TTL and low voltage CMOS compatible I/Os
• +3V to +5.5V operation (VDD - VSS)
• LS7183, LS7184 (DIP);
V DD (+V ) 2
7 _DNCK
LS7183-S, LS7184-S (SOIC) - See Figure 1
V SS (-V ) ³
6 ^MODE
Applications:
• Interface incremental encoders to Up / Down Counters
(See Figure 6A and Figure 6B)
• Interface rotary encoders to Digital Potentiometers
d _{(See Figure 7)}
A4
5B
e DESCRIPTION:
The LS7183 and LS7184 are CMOS quadrature clock converters.
Quadrature clocks derived from optical or magnetic encoders, when
u _{applied to the A and B inputs of the LS7183/LS7184, are converted to}
strings of Up Clocks and Down Clocks (LS7183) or to a Clock and an
tin ^{Up/Down direction control (LS7184). These outputs can be interfaced}
directly with standard Up/Down counters for direction and position
INPUT/OUTPUT DESCRIPTION:
RBIAS (Pin 1)
n _{Input for external component connection. A resistor connected be-}
tween this input and VSS adjusts the output clock pulse width (Tow).
RBIAS 1
V DD (+V ) ₂
V SS (-V ) 3
A4
8 CLK
7 _UP/DN
6 MODE
5B
FIGURE 1
o _{VDD (Pin 2)}
c ^{Supply Voltage positive terminal.}
is ^{VSS (Pin 3)}
Supply Voltage negative terminal.
LS7183 - DNCK (Pin 7)
In LS7183, this is the DOWN Clock Output. This output con-
sists of low-going pulses generated when A input lags the B
input.
A, B (Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are gener-
D _{ated from the A and B clocks according to Fig. 2. A and B inputs have}
built-in immunity for noise signals less than 50ns duration (Validation
delay, TVD). The A and B inputs are inhibited during the occurrence of
a directional output clock (UPCK or DNCK), so that spurious clocks
LS7184 - UP/DN (Pin 7)
In LS7184, this is the count direction indication output. When
A input leads the B input, the UP/DN output goes high in-
dicating that the count direction is UP. When A input lags the
B input, UP/DN output goes low, indicating that the count di-
rection is DOWN.
resulting from encoder dither are rejected.
LS7183 - UPCK (Pin 8)
MODE (Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The input
In LS7183, this is the UP Clock output. This output consists of
low-going pulses generated when A input leads the B input.
quadrature clock rate is multiplied by factors of 1, 2 and 4 in x1, x2
and x4 mode, respectively, in producing the output UP/DN clocks
(See Fig. 2). x1, x2 and x4 modes selected by the MODE input logic
levels are as follows:
LS7184 - CLK (Pin 8)
In LS7184, this is the combined UP Clock and DOWN Clock
output. The count direction at any instant is indicated by the
UP/DN output (Pin 7).
Mode = 0 : x1 selected
Mode = 1 : x2 selected
Mode = Float : x4 selected
NOTE: For the LS7184, the timing of CLK and UP/DN re-
quires that the counter interfacing with LS7184 counts on the
rising edge of the CLK pulses.
7183/84-011309-1