LS7183N Datasheet, PDF (1/4 Pages) LSI Computer Systems – QUADRATURE CLOCK CONVERTER

LSI/CSI
LS7183N
LS7184N
U_{® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]}
A3800
QUADRATURE CLOCK CONVERTER
April 2009
FEATURES:
• x1, x2 and x4 resolution
• Programmable output pulse width (200ns to 140µs)
• Excellent regulation of output pulse width
• TTL and low voltage CMOS compatible I/Os
• +3V to +12V operation (VDD - VSS)
• LS7183N, LS7184N (DIP);
LS7183N-S, LS7184N-S (SOIC) - See Figure 1
Applications:
• Interface incremental encoders to Up / Down Counters
(See Figure 6A and Figure 6B)
• Interface rotary encoders to Digital Potentiometers
(See Figure 7)
PIN ASSIGNMENT - TOP VIEW
RBIAS ¹
V DD (+V ) 2
V SS (-V ) ³
A4
8 _UPCK
7 _DNCK
6 ^MODE
5B
DESCRIPTION:
The LS7183N and LS7184N are CMOS quadrature clock converters.
Quadrature clocks derived from optical or magnetic encoders, when
applied to the A and B inputs of the LS7183N / LS7184N, are con-
verted to strings of Up Clocks and Down Clocks (LS7183N) or to a
Clock and an Up/Down direction control (LS7184N). These outputs
can be interfaced directly with standard Up/Down counters for direc-
tion and position sensing of the encoder.
INPUT/OUTPUT DESCRIPTION:
RBIAS (Pin 1)
Input for external component connection. A resistor connected be-
tween this input and VSS adjusts the output clock pulse width (Tow).
RBIAS 1
V DD (+V ) ₂
V SS (-V ) 3
8 CLK
7 _UP/DN
6 MODE
A4
5B
FIGURE 1
VDD (Pin 2)
Supply Voltage positive terminal.
VSS (Pin 3)
Supply Voltage negative terminal.
LS7183N - DNCK (Pin 7)
In LS7183N, this is the DOWN Clock Output. This output con-
sists of low-going pulses generated when A input lags the B
input.
A, B (Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are gener-
ated from the A and B clocks according to Fig. 2. A and B inputs have
built-in immunity for noise signals less than 50ns duration (Validation
delay, TVD). The A and B inputs are inhibited during the occurrence of
a directional output clock (UPCK or DNCK), so that spurious clocks
resulting from encoder dither are rejected.
MODE (Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The input
quadrature clock rate is multiplied by factors of 1, 2 and 4 in x1, x2
and x4 mode, respectively, in producing the output UP/DN clocks
(See Fig. 2). x1, x2 and x4 modes selected by the MODE input logic
levels are as follows:
Mode = 0 : x1 selected
Mode = 1 : x2 selected
Mode = Float : x4 selected
LS7184N - UP/DN (Pin 7)
In LS7184N, this is the count direction indication output.
When A input leads the B input, the UP/DN output goes high
indicating that the count direction is UP. When A input lags
the B input, UP/DN output goes low, indicating that the count
direction is DOWN.
LS7183N - UPCK (Pin 8)
In LS7183N, this is the UP Clock output. This output consists
of low-going pulses generated when A input leads the B in-
put.
LS7184N - CLK (Pin 8)
In LS7184N, this is the combined UP Clock and DOWN
Clock output. The count direction at any instant is indicated
by the UP/DN output (Pin 7).
NOTE: For the LS7184N, the timing of CLK and UP/DN re-
quires that the counter interfacing with LS7184N counts on
the rising edge of the CLK pulses.
7183N/84N-042709-1