LS7183 Datasheet, PDF (1/4 Pages) LSI Computer Systems – QUADRATURE CLOCK CONVERTER

LSI/CSI
LS7183/LS7184
U_{® L LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]}
A3800
QUADRATURE CLOCK CONVERTER
August 2001
FEATURES:
• x1, x2 and x4 resolution
• Programmable output pulse width (200ns to 140µs)
• Excellent regulation of output pulse width
• TTL and low voltage CMOS compatible I/Os
• +3V to +5.5V operation (VDD-VSS)
• LS7183, LS7184 (DIP)
LS7183-S, LS7184-S (SOIC) - See Figure 1
DESCRIPTION:
The LS7183 and LS7184 are monolithic CMOS silicon gate
quadrature clock converters. Quadrature clocks derived from
optical or magnetic encoders, when applied to the A and B
inputs of the LS7183/LS7184, are converted to strings of Up
Clocks and Down Clocks (LS7183) or to a Clock and an Up/
Down direction control (LS7184). These outputs can be in-
terfaced directly with standard Up/Down counters for direc-
tion and position sensing of the encoder.
PIN ASSIGNMENT - TOP VIEW
RBIAS 1
VDD(+V) ₂
VSS(-V) 3
A4
8 UPCK
7 _DNCK
6 MODE
5
B
RBIAS
1
VDD(+V)
2
8 ^CLK
7 _UP/DN
INPUT/OUTPUT DESCRIPTION:
RBIAS (Pin 1)
Input for external component connection. A resistor connected
between this input and VSS adjusts the output clock pulse
width (Tow).
VDD (Pin 2)
Supply Voltage positive terminal.
VSS (Pin 3)
Supply Voltage negative terminal.
VSS(-V) 3
A4
6 MODE
5B
FIGURE 1
LS7183 - DNCK (Pin 7)
In LS7183, this is the DOWN Clock Output. This output
consists of low-going pulses generated when A input
lags the B input.
A, B (Pin 4, Pin 5)
Quadrature Clock inputs A and B. Directional output pulses are
generated from the A and B clocks according to Fig. 2. A and B
inputs have built-in immunity for noise signals less than 50ns
duration (Validation delay, TVD). The A and B inputs are in-
hibited during the occurrence of a directional output clock
(UPCK or DNCK), so that spurious clocks resulting from en-
coder dither are rejected.
MODE (Pin 6)
MODE is a 3-state input to select resolution x1, x2 or x4. The
input quadrature clock rate is multiplied by factors of 1, 2 and 4
in x1, x2 and x4 mode respectively in producing the output
UP/DN clocks (See Fig. 2). x1, x2 and x4 modes selected by
the MODE input logic levels are as follows:
Mode = 0 : x1 selected
Mode = 1 : x2 selected
Mode = Float : x4 selected
LS7184LV - UP/DN (Pin 7)
In LS7184, this is the count direction indication output.
When A input leads the B input, the UP/DN output goes
high indicating that the count direction is UP. When A
input lags the B input, UP/DN output goes low,
indicating that the count direction is DOWN.
LS7183 - UPCK (Pin 8)
In LS7083LV, this is the UP Clock output. This output
consists of low-going pulses generated when A input
leads the B input.
LS7184 - CLK (Pin 8)
In LS7184, this is the combined UP Clock and DOWN
Clock output. The count direction at any instant is
indicated by the UP/DN output (Pin 7).
NOTE: For the LS7184, the timing of CLK and UP/DN
requires that the counter interfacing with LS7184 counts
on the rising edge of the CLK pulses.
7183/84-071201-1