LS7166_08 Datasheet, PDF (1/19 Pages) LSI Computer Systems – 24-BIT QUADRATURE COUNTER

LSI/CSI
LS7166
U_{® L}
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]
A3800
24-BIT QUADRATURE COUNTER
December 2008
FEATURES:
• Programmable modes are: Up/Down,
Binary, BCD, 24 Hour Clock, Divide-by-N,
x1 or x2 or x4 Quadrature and Single-Cycle.
• DC to 25MHz Count Frequency.
• 8-Bit I/O Bus for uP Communication and Control.
• 24-Bit comparator for pre-set count comparison.
• Readable status register.
• Input/Output TTL and CMOS compatible.
• 3V to 5.5V operation (VDD - VSS).
• LS7166 (DIP); LS7166-S (SOIC);
LS7166-TS24 (24-Pin TSSOP) - See Figure 1 -
GENERAL DESCRIPTION:
The LS7166 is a CMOS, 24-bit counter that can be pro-
grammed to operate in several different modes. The oper-
ating mode is set up by writing control words into internal
control registers (see Figure 8). There are three 6-bit and
one 2-bit control registers for setting up the circuit functional
characteristics. In addition to the control registers, there is a
5-bit output status register (OSR) that indicates the current
counter status. The IC communicates with external circuits
through an 8-bit three state I/O bus. Control and data words
are written into the LS7166 through the bus. In addition to
the I/O bus, there are a number of discrete inputs and out-
puts to facilitate instantaneous hardware based control func-
tions and instantaneous status indication.
REGISTER DESCRIPTION:
Internal hardware registers are accessible through the I/O
bus (D0 - D7) for READ or WRITE when CS = 0. The C/D in-
put selects between the control registers (C/D = 1) and the
data registers (C/D = 0) during a READ or WRITE operation.
(See Table 1)
The information included herein is believed to be
accurate and reliable. However, LSI Computer Systems,
Inc. assumes no responsibilities for inaccuracies, nor for
any infringements of patent rights of others which may
result from its use.
PIN ASSIGNMENTS - Top View
20-PIN
DIP and SOIC
WR ¹
20 VSS ( -V )
CS ₂
LCTR/LLTC 3
19 RD
18 C/D
ABGT/RCTR 4
17 ^BW
VDD ( +V) 5
16 CY
A6
15 D7
B7
14 D6
D0 8
13 D5
D1 9
12 D4
D2 10
11 D3
WR 1
CS ²
LCTR/LLTC
3
ABGT/RCTR
4
NC 5
NC ₆
NC 7
A8
B9
D0 10
D1 11
D2 12
24-PIN
TSSOP
24 VSS ( - V )
23 RD
22 C/D
21 ^{VDD ( +V)}
20 BW
19 CY
18 NC
17 D7
16 D6
15 D5
14 D4
13 D3
FIGURE 1
7166-121508-1