LS7082 Datasheet, PDF (1/4 Pages) LSI Computer Systems – QUADRATURE CLOCK CONVERTER

LSI/CSI
LS7082
U_{® L}
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]
A3800
QUADRATURE CLOCK CONVERTER
October 2000
FEATURES:
• x1, x2 and x4 mode selection
• Up to 16 MHz output clock frequency
• INDEX input and output
• UP/DOWN indicator output
• Programmable output clock pulse width
• On-chip filtering of inputs for optical or
magnetic encoder applications.
• TTL and CMOS compatible I/Os
• +4.5V to +10.0V operation (VDD-VSS)
• LS7082 (DIP); LS7082-S (SOIC ) - See Figure 1
DESCRIPTION:
The LS7082 is a monolithic CMOS silicon gate quadrature
clock converter. Quadrature clocks derived from optical or
magnetic encoders, when applied to the A and B Inputs of the
LS7082, are converted to strings of Up Clocks and Down
Clocks. Pulses derived from the Index Track of an encoder,
when applied to the INDX input, produce absolute position ref-
erence pulses which are synchronized to the Up Clocks and
Down Clocks. These outputs can be interfaced directly with
standard Up/Down counters for direction and position sensing
of the encoder.
INPUT/OUTPUT DESCRIPTION:
VDD (Pin 1)
Supply Voltage positive terminal.
PIN ASSIGNMENT - TOP VIEW
V DD (+V) 1
INDX ²
RBIAS ³
V SS (-V) 4
A5
NC ₆
NC ⁷
FIGURE 1
14 ^INDX
13 UPCK
12 ^DNCK
11 U P / D N
10 x 4 / x 1
9
B
8
x2
TABLE 1. MODE SELECTION TRUTH TABLE
x2 Input
0
1
1
x4/x1 Input
Don’t Care
0
1
MODE
x2
x1
x4
INDX (Pin 2)
Encoder Index pulses are applied to this input.
RBIAS (Pin 3)
Input for external component connection. A resistor con-
nected between this input and VSS adjusts the output clock
pulse width (Tow). For proper operation, the output clock
pulse width must be less than or equal to the A,B pulse
separation (TOW ≤ TPS).
x4/x1 (Pin 10)
This input selects between x1 and x4 modes of operation.
See Table 1 for Mode Selection Truth Table and Figure 2
for Input/Output timing relationship.
UP/DN (Pin 11)
The count direction at any instant is indicated at this out-
put. An UP count direction is indicated by a high, and a
DOWN count direction is indicated by a low (See Figure 2).
VSS (Pin 4)
Supply Voltage negative terminal.
A (Pin 5)
Quadrature Clock Input A. This input has a filter circuit to
validate input logic level and eliminate encoder dither.
x2 (Pin 8)
A low level applied to this input selects x2 mode of opera-
tion. See Table 1 for Mode Selection Truth Table and
Figure 2 for Input/Output timing relationship.
B (Pin 9)
Quadrature Clock Input B. This input has a filter circuit
identical to input A.
DNCK (Pin 12)
This DOWN Clock output consists of low-going pulses gen-
erated when A input lags the B input (See Figure 2).
UPCK (Pin 13)
This UP Clock output consists of low-going pulses gener-
ated when A input leads the B input (See Figure 2).
INDX (Pin 14)
This output consists of low-going pulses generated by
clock transitions at the A input when INDX input is high and
B input is low (See Figure 2).
NOTE: All unused input pins must be tied to VDD or VSS.
7082-100600-1