LS7031_03 Datasheet, PDF (1/4 Pages) LSI Computer Systems – 6 DECADE MOS UP COUNTER WITH 8 DECADE LATCH AND MULTIPLEXER

LSI/CSI
LS7031
U_{® L}
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 [phone] FAX [phone]
A3800
6 DECADE MOS UP COUNTER WITH 8 DECADE LATCH AND MULTIPLEXER
FEATURES:
• DC to 7.5 MHz Count Frequency
• Multiplexed BCD Outputs
• DC to 500kHz Scan Frequency
• +4.75V to +15V Operation (VDD - VSS)
• Compatible with CMOS Logic
• High Input Noise Immunity
• Ability to Latch External BCD Data in the two LSD Positions
• Leading Zero Blanking with Decimal Point and Overflow Controls
• All inputs protected
• Low Power Dissipation
• 40 Pin DIP - See Figure 1
January 2003
CONNECTION DIAGRAM - TOP VIEW
SCAN RESET INPUT ¹
MSD STROBE 8 2
STROBE 7 ₃
STROBE 6 4
DIGIT
STROBE
OUTPUTS
STROBE 5 5
STROBE 4 6
STROBE 3 7
STROBE 2 8
40 OSC. INPUT
39 SCAN INPUT
38 N.C.
37 B 1 / D 1
36 B 2 / D 1
35 N.C.
34 ^{B 4 / D 1}
INPUT TO
DECADE 1
LATCH
33 B 8 / D 1
DESCRIPTION: (See Block Diagram, Figure 4.)
The LS7031 is a MOS, 6 decade up counter. The circuit includes
latches, a multiplexer, leading zero blanking and BCD data outputs.
CLOCK GENERATOR
The clock for the six decade counter (digit positions 3-8) is formed
from the internal ‘OR’ combination of B4/D2 and B8/D2 if LS7031
is used with external prescaling counters. When operated in this
fashion the maximum allowable propagaton delay between B4/D2
(H-L) and B8/D2 (L-H), measured at Vss - 1V, is 10ns. If used as
a straight six decade counter, clock pulses may be applied to
inputs B4/D2 or B8/D2 with the unused input held low. In either
mode of operation total pulse width must be minimum 62ns.
LSD STROBE 1 9
DECIMAL POINT INPUT ₁₀
BLANK OUTPUT ₁₁
OVERFLOW OUTPUT 12
OVERFLOW INPUT 13
DECADE 8 OUTPUT, D8 ₁₄
DECADE 7 OUTPUT, D7 15
DECADE 6 OUTPUT, D6 ₁₆
BCD
DATA
OUTPUTS
B8 ₁₇
B4 18
B2 19
LS7031
32 N.C.
31 B 1 / D 2
30 B 2 / D 2
29 ^{B 4 / D 2}
28 ^{B 8 / D 2}
INPUT TO
DECADE 2
LATCH
27 V SS
26 V GG
25 N.C.
24 _N.C.
23 V DD
22 RESET COUNTER INPUT
6 DECADE UP COUNTER
B1 ²⁰
21 LOAD LATCH INPUT
The six decade ripple through counter increments on the negative
edge of the input count pulse. Maximum ripple time is 12µs
FIGURE 1
(999999 to 000000). Maximum count frequency is 7.5MHz.
DIGIT STROBES
Timing of Digit Strobes is arranged such that both edges of strobe
RESET
are guardbanded by a minimum 400ns within valid BCD data when
All 6 counter decades are reset to zero when Reset input is brought scan frequency is 100kHz or less. The guardband is a minimum of
low for a minimum of 4µs. The Overflow flip-flop is reset at the
200ns at 250kHz scan frequency. At 500kHz only negative edge of
same time. Reset must be high for a minimum of 1µs before next Strobe is guaranteed to be within valid BCD data by a minimum
valid count can be recorded.
200ns.
SCAN OSCILLATOR AND COUNTER
The scan counter is driven by an internal oscillator whose
frequency is determined by a capacitor connected between
Oscillator input and Scan input. An external scan clock applied
to Scan input can also drive the scan counter. Scan counter
advances on negative edge of scan clock.
The counter scans from MSD to LSD. When Scan Reset input is
brought high the scan counter is forced to MSD state. Internal
synchonization guarantees proper scanning no matter when Scan
Reset is brought low relative to scan clock. Maximum scan
frequency is 500kHz.
DECIMAL POINT
A high at the Decimal Point input resets the Blanking flip-flop
causing the display to unblank. Decimal Point should be brought
high at start of digit time which has active Decimal Point.
OVERFLOW
The Overflow flip-flop sets on the first negative transition of the Over-
flow Input and remains set until Reset is brought low. Data is trans-
ferred from Overflow flip-flop to Overflow Latch when Load is brought
low. A high at the Overflow Latch causes display to unblank. Over-
flow Output is output of Overflow Latch. MSB outputs of Decades
6, 7, 8 are available for use as Overflow Input.
LATCHES
Eight decades of latch are provided, two for storage of the two
external least significant decade counters and the remaining 6 for in-
ternal counter outputs. All latches when Load signal is brought low
for a minimum of 4µs and kept low until a minimum of 12µs has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when Load signal is high for a minimum
of 1µs before next negative edge of count pulse or reset. Data is
transferred from Overflow flip-flop to Overflow latch at the same time.
7031-012703-1