L74VHC1GT03 Datasheet, PDF (1/6 Pages) Leshan Radio Company – 2-Input NOR Gate with Open Drain Output with LSTTL-Compatible Inputs

LESHAN RADIO COMPANY, LTD.
2–Input NOR Gate with Open Drain Output
with LSTTL–Compatible Inputs
L74VHC1GT03
The L74VHC1GT03 is an advanced high speed CMOS 2–input NOR gate with an open drain output fabricated with silicon gate
CMOS technology. It achieves high speed peration similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including an open drain output which provides the ability to set output switching level.
This allows the L74VHC1GT03 to be used to interface 5 V circuits to circuits of any voltage between V CC and 7 V using an external
resistor and power supply.
The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The L74VHC1GT03 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the L74VHC1GT03 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V _CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: t PD = 3.6 ns (Typ) at V CC = 5 V
• Low Internal Power Dissipation: I CC = 2 mA (Max) at T A = 25°C
• Power Down Protection Provided on Inputs
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 62; Equivalent Gates = 16
5
4
MARKING DIAGRAMS
1
2
3
SC–88A / SOT–353/SC–70
DF SUFFIX
5
4
VP^d
Pin 1
d = Date Code
Figure 1. Pinout (Top View)
1
2
3
TSOP–5/SOT–23/SC–59
DT SUFFIX
PIN ASSIGNMENT
1
IN B
2
IN A
3
GND
4
OUT Y
5
V CC
VP^d
Pin 1
d = Date Code
Figure 2. Logic Symbol
FUNCTION TABLE
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
Z
L
L
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
1/6