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L74VHC1GT01 Datasheet, PDF (1/6 Pages) Leshan Radio Company – 2-Input NAND Gate with Open Drain Output with LSTTL-Compatible Inputs | |||
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LESHAN RADIO COMPANY, LTD.
2âInput NAND Gate with Open Drain Output
with LSTTLâCompatible Inputs
L74VHC1GT01
The L74VHC1GT01 is an advanced high speed CMOS 2âinput NAND gate with an open drain output fabricated with silicon gate
CMOS technology. It achieves high speed peration similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including an open drain output which provides the ability to set output switching level.
This allows the L74VHC1GT01 to be used to interface 5 V circuits to circuits of any voltage between V CC and 7 V using an external
resistor and power supply.
The device input is compatible with TTLâtype input thresholds and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logicâlevel translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the highâvoltage power
supply.
The L74VHC1GT01 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the L74VHC1GT01 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage â input/output voltage mismatch,
battery backup, hot insertion, etc.
⢠High Speed: t PD = 3.7 ns (Typ) at V CC = 5 V
⢠Low Internal Power Dissipation: I CC = 2 mA (Max) at T A = 25°C
⢠Power Down Protection Provided on Inputs
⢠Pin and Function Compatible with Other Standard Logic Families
⢠Chip Complexity: FETs = 62; Equivalent Gates = 16
MARKING DIAGRAMS
5
4
1
2
3
SCâ88A / SOTâ353/SCâ70
DF SUFFIX
5
4
V0d
Pin 1
d = Date Code
Figure 1. Pinout (Top View)
1
2
3
TSOPâ5/SOTâ23/SCâ59
DT SUFFIX
PIN ASSIGNMENT
1
IN B
2
IN A
3
GND
4
OUT Y
5
V CC
V0d
Figure 2. Logic Symbol
Pin 1
d = Date Code
FUNCTION TABLE
Inputs
A
B
L
L
L
H
H
L
H
H
Output
Y
Z
Z
Z
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 5 of this data sheet.
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