L9D320G32BG6 Datasheet, PDF (77/154 Pages) LOGIC Devices Incorporated – 2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)

ADVANCE INFORMATION L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN
CK#
CK
CKE
Command
Previous clock frequency
T0
T1
T2
t _CH
t _CL
t _CK
t _IH
t _IS
t _CKSRE
NOP
t _CPDED
NOP
NOP
Address
ODT
DQS, DQS#
DQ
DM
t _AOFPD/ t _AOF
High-Z
High-Z
Enter precharge
power-down mode
Ta0
Tb0
t _CKE
Tc0
Tc1
t _CHb t _CLb
t _CKb
t _CKSRX
t _IH
t _IS
NOP
New clock fre quency
Td0
Td1
t _CHb
t _CLb
t _CKb
Te0
Te1
t _CHb t _CLb
t _CKb
NOP
t _XP
MRS
DLL RESET
NOP
t _IH
Valid
Valid
t _IS
Frequency
change
Exit precharge
power-down mode
t _DLLK
Indicates a Break in
Time Scale
Don’t Care
NOTES:
1. Applicable for both slow-exit and fast-exit precharge power-down modes.
2. t_{AOFPD and} t_{AOF must be satisfied and outputs High-Z prior to T1 (see “On-Die Termination}
(ODT)” on page 161 for exact requirements).
3. If the RTT_NOM feature was enabled in the mode register prior to entering precharge power-down
mode, the ODT signal must be continuously registered LOW ensuring RTT is in an off state. If
the RTT_NOM feature was disabled in the mode register prior to entering precharge power-down
mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in
this case.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
77
Jul 08, 2009 LDS-L9D320G32BG6-A