LF3310 Datasheet, PDF (5/21 Pages) LOGIC Devices Incorporated – Horizontal / Vertical Digital Image Filter

DEVICES INCORPORATED
LF3310
Horizontal / Vertical Digital Image Filter
HRSL3-0 — Horizontal Round/Select/
Limit Control
HRSL3-0 determines which of the
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the horizontal Round/
Select/Limit circuitry (RSL circuitry).
A value of 0 on HRSL3-0 selects
RSL register 0. A value of 1 selects
round/select/limit register 1 and so
on. HRSL3-0 is latched on the rising
edge of CLK (see the horizontal
round, select, and limit sections for a
complete discussion).
FIGURE 4. DIMENSIONALLY SEPARATE MODE: H TO V
12
DIN11-0
HORIZONTAL FILTER
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
12
DOUT11-0
VRSL3-0 —Vertical Round/Select/Limit
Control
VRSL3-0 determines which of the
sixteen user-programmable
RSL registers are used in the vertical
RSL circuitry. A value of 0 on
VRSL3-0 selects RSL register 0. A
value of 1 selects RSL register 1 and
so on. VRSL3-0 is latched on the rising
edge of CLK (see the vertical round,
select, and limit sections for a com-
plete discussion).
LINE BUFFER
LINE BUFFER
LINE BUFFER
FIGURE 5. DIMENSIONALLY SEPARATE MODE: V TO H
12
DIN11-0
LINE BUFFER
LINE BUFFER
OE — Output Enable
When OE is LOW, DOUT11-0 is
enabled for output. When OE is
HIGH, DOUT11-0 is placed in a
high-impedance state.
LINE BUFFER
12
HORIZONTAL FILTER
LINE BUFFER
LINE BUFFER
12
LINE BUFFER
HPAUSE — LF Interface^TM Pause
LINE BUFFER
DOUT11-0
When HPAUSE is HIGH, the Hori-
zontal LF Interface^TM loading
sequence is halted until HPAUSE is
returned to a LOW state. This
effectively allows the user to load
coefficients and Control Registers at a
slower rate than the master clock (see
the LF Interface^TM section for a full
discussion).
VPAUSE — LF Interface^TM Pause
When VPAUSE is HIGH, the Vertical
LF Interface^TM loading sequence is
halted until VPAUSE is returned to a
LOW state. This effectively allows the
user to load coefficients and Control
Registers at a slower rate than the
master clock (see the LF Interface^TM
section for a full discussion).
OPERATIONAL MODES
Dimensionally Separate
In Dimensionally Separate Mode, the
horizontal and vertical filters are
cascaded together to form a
two-dimensional image filter (see
Figures 4 and 5). Bit 1 in Configura-
tion Register 4 determines the cascade
order. If this bit is set to “0”, data on
DIN11-0 is fed into the horizontal filter
first. The horizontal filter then feeds
data into the vertical filter. If this bit
is set to “1”, data on DIN11-0 is fed
into the vertical filter first. The
vertical filter then feeds data into the
horizontal filter.
Orthogonal
In Orthogonal Mode, the horizontal
and vertical filters are used concur-
rently to implement an orthogonal
kernel on the input data (see Figure 6).
Video Imaging Products
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11/08/2001-LDS.3310-H