LF3338 Datasheet, PDF (4/15 Pages) LOGIC Devices Incorporated – 8-Bit Vertical Digital Image Filter

DEVICES INCORPORATED
LF3338
8-Bit Vertical Digital Image Filter
TABLE 2. CONFIGURATION REGISTER 0 – ADDRESS 200H
BITS FUNCTION
DESCRIPTION
11-0 Line Buffer Length
See Line Buffer Description Section
TABLE 3. CONFIGURATION REGISTER 1 – ADDRESS 201H
BITS FUNCTION
DESCRIPTION
0
Line Buffer Mode
0 : Delay Mode
1 : Recirculate Mode
1
Line Buffer Load
0 : Normal Load
1 : Parallel Load
2
Odd and Even Field
0 : VB Port Disabled
Filtering Port Enable
1 : VB Port Enabled
3
Odd and Even Field
0 : VB Line Buffer Disabled
Filtering Line Buffer Enable 1 : VB Line Buffer Enabled
11-4 Reserved
Must be set to “0”
FIGURE 4. RSL CIRCUITRY
RSL3-0
4
DATA IN
32
32
RND
32
5
SELECT
TABLE 4. CONFIGURATION REGISTER 2 – ADDRESS 202H
BITS FUNCTION
DESCRIPTION
0
Limit Enable
0 : Limiting Disabled
1 : Limiting Enabled
11-1 Reserved
Must be set to “0”
16
32
LIMIT
TABLE 5. CONFIGURATION REGISTER 3 – ADDRESS 203H
BITS FUNCTION
DESCRIPTION
0
Cascade Mode
0 : First Device
1 : Cascaded Device
11-1 Reserved
Must be set to “0”
RSL CIRCUITRY
16
DATA OUT
ACC — Accumulator Control
When ACC is HIGH, the accumulator
is enabled for accumulation and the
accumulator output register is
disabled for loading. When ACC is
LOW, no accumulation is performed
and the accumulator output register
is enabled for loading. ACC is
latched on the rising edge of CLK.
SHEN — Shift Enable
SHEN enables or disables the
loading of data into the input/
cascade registers and the line
buffers. When SHEN is LOW, data
is loaded into the input/cascade
registers and shifted through the
line buffers on the rising edge of
CLK. When SHEN is HIGH, data
can not be loaded into the input/
cascade registers or shifted through
the line buffers and their contents
will not be changed.
RSL3-0 — Round/Select/Limit Control
RSL3-0 determines which of the
sixteen user-programmable round/
select/limit registers are used in the
round/select/limit circuitry. A
value of 0 on RSL3-0 selects round/
select/limit register 0. A value of 1
selects round/select/limit register 1
and so on. RSL3-0 is latched on the
rising edge of CLK (see the round,
select, and limit sections for a
complete discussion).
OED — DOUT Output Enable
When OED is LOW, DOUT15-0 is
enabled for output. When OED is
HIGH, DOUT15-0 is placed in a
high-impedance state.
OEC — COUT Output Enable
When OEC is LOW, COUT7-0 is
enabled for output. When OEC is
HIGH, COUT7-0 is placed in a high-
impedance state.
Video Imaging Products
4
04/06/1999–LDS.3338-B