LF48212 Datasheet, PDF (3/9 Pages) LOGIC Devices Incorporated – 12 x 12-bit Alpha Mixer

DEVICES INCORPORATED
LF48212
12 x 12-bit Alpha Mixer
FUNCTIONAL DESCRIPTION
The two video signals to be mixed
together are input to the LF48212
using DINA11-0 and DINB11-0. Data
present on DINA11-0 and DINB11-0 is
latched on the rising edge of CLK.
The input data may be in either
unsigned or two’s complement
format, but both inputs must be in the
same format. TC determines the
format of the input data. When TC is
HIGH, the input data is in unsigned
format. When TC is LOW, the input
data is in two’s complement format.
TC is latched on the rising edge of
CLK and only affects the input data
latched in at the same time. The data
already in the pipeline is not affected
when TC changes.
DINA11-0 and DINB11-0 are mixed
together using an alpha mix factor
α( 11-0) as defined by the equation
listed in Figure 2. α11-0 is unsigned
and restricted to the range of 0 to 1.0.
MIXEN controls the loading of alpha
mix data. When MIXEN is HIGH,
data present on α11-0 is latched on the
rising edge of CLK. When MIXEN is
LOW, data present on α11-0 is not
latched and the last value loaded is
held as the alpha mix value.
It is possible to add extra delay stages
to the input data and control signals
by using the programmable delay
stages. The 15-bit value (DELAY14-0)
stored in the Delay Control Register
determines the number of delay stages
added. DELAY14-0 is divided into 5
groups of 3-bits each. Each 3-bit
group contains the delay information
for one of the input data or control
signals. Figure 3 shows the block
diagram of the Delay Control Register
as well as a list of the input data and
control signals that may be delayed
and the DELAY signals that control
them. The delay length can be pro-
grammed to be from 0 to 7 stages. The
delay length is set by loading the
binary equivalent of the desired delay
length into the appropriate 3-bit
group. For example, to add four extra
delay stages to DINB11-0, DELAY5-3
should be set to “100”. DELAY14-0 is
loaded serially into the Delay Control
Register using DEL and LD. DELAY0
is the first value loaded and DELAY14
is the last. Data present on DEL is
latched on the rising edge of LD.
BYPASS is used to disable the pro-
grammable delay stages. When
BYPASS is HIGH, the Delay Control
Register is automatically loaded with
a “0”. This sets all programmable
delay stages to a length of zero. When
BYPASS is LOW, the Delay Control
Register may be loaded to set the
desired number of delay stages. Note
that BYPASS is not intended to change
during active operation of the
LF48212.
The Adjust stage of the LF48212 is
used to maximize the precision of the
output data. Since α can never be
larger than 1.0, the most significant bit
of the internal summer output is not
needed. The Adjust stage takes the
output of the internal summer and left
shifts the data one bit position. This
removes the MSB of the internal
summer output and provides one
more bit of precision for the output
data.
The output data of the LF48212 may
be rounded to 8, 10, 12, or 13-bits.
RND1-0 determines how the output is
rounded (See Table 1). RND1-0 is
latched on the rising edge of CLK and
only affects the input data latched in
at the same time. The data already in
the pipeline is not affected when
RND1-0 changes.
FIGURE 2. OUTPUT EQUATION
OUTPUT = α(DINA) + (1 – α)DINB
FIGURE 3. DELAY CONTROL REGISTER BLOCK DIAGRAM
DEL
LD
DQ
LD
DQ
LD
DQ
DELAY14
DELAY13
DELAY12
RND1-0 DELAY
DQ
LD
DQ
LD
DQ
DELAY11
DELAY10
DELAY9
TC DELAY
DQ
LD
DQ
LD
DQ
DELAY8
DELAY7
DELAY6
α11-0 DELAY
DQ
LD
DQ
LD
DQ
DELAY5
DELAY4
DELAY3
DINB11-0 DELAY
DQ
LD
DQ
LD
DQ
DELAY2
DELAY1
DELAY0
DINA11-0 DELAY
Video Imaging Products
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08/16/2000–LDS.48212-F