LF2249 Datasheet, PDF (3/8 Pages) LOGIC Devices Incorporated – 12 x 12-bit Digital Mixer

DEVICES INCORPORATED
LF2249
12 x 12-bit Digital Mixer
Outputs
NEG1–NEG2 — Negate Control
ACC — Accumulator Control
S15-0 — Data Output
The NEG1 and NEG2 controls deter- The ACC input determines whether in-
The current 16-bit result is available
on the S15-0 outputs. The output data
may be either the upper or lower 16
bits of the accumulator output, de-
pending on the state of SWAP. The
LSB is S0 (Figure 1b).
mine whether a subtraction or accumu-
lation of products is performed. When
NEG1 is HIGH, the product A x B is
negated, causing the product to be sub-
tracted from the accumulator contents.
Likewise, when NEG2 is HIGH, the
product C x D is negated, causing the
product to be subtracted as well. NEG1
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
products is output. When ACC is
HIGH, the emerging products are
added to the sum of the previous prod-
1
2
Controls
and NEG2 determine the operation to ucts.
ENA–END — Pipeline Register Enable
Input data in the N (N = A, B, C, or D)
be performed on the data input during
the current clock cycle when ADEL–
DDEL = 0000.
RND — Rounding Control
3
input register is latched into the corre-
When RND is HIGH, the sum of the
sponding pipeline register stack on
each rising edge of CLK for which ENN
CASEN — Cascade Enable
products of the data being input on
the current clock cycle will be
4
is LOW. Data already in the N register When CASEN is LOW, data being in- rounded to 16 bits. To avoid the accu-
stack is pushed down one register posi- put on the CAS15-0 inputs during that mulation of roundoff errors, round-
tion. When ENN is HIGH, the data in clock cycle will be registered and accu- ing is only performed during the first
5
the N pipeline register stack does not mulated internally. When CASEN is cycle of each accumulation process.
change, and the data in the N input HIGH, the CAS15-0 inputs are ignored.
register will not be stored in the register
stack.
FT — Feedthrough Control
SWAP — Output Select
6
The SWAP control allows the user to
ADEL3-0–DDEL3-0 — Pipeline Delay
Select
When FT is LOW and ADEL–DDEL = access all 24 bits of the accumulator
0000, data being input on the CAS15-0 output by switching between upper
7
inputs is delayed three clock cycles to and lower 16-bit words. When SWAP
NDEL (N = A, B, C, or D) is the 4-bit align the data with the data being input is HIGH, the upper 16 bits of the accu-
registered pipeline delay select word. on the A11-0–D11-0 inputs. When FT is mulator are always output. When
8
NDEL determines which stage of the N HIGH, the cascade data being input is SWAP is LOW, the lower 16 bits of the
pipeline register stack is routed to the routed around the three delay registers accumulator are output on every
9 ^{multiplier inputs. The minimum delay to simplify the cascading of multiple other clock cycle. As long as SWAP}
is one clock cycle (NDEL = 0000), and devices.
remains LOW, new output data will
the maximum delay is 16 clock cycle
not be clocked into the output regis-
(NDEL = 1111). Upon power up, the
values of ADEL–DDEL and the con-
ters.
10
tents of the pipeline register stacks are
unknown and must be initialized by the
user.
OE — Output Enable
11 When the OE signal is LOW, the
current data in the output registers
is available on the S15-0 pins. When
OE is HIGH, the outputs are in a
high-impedance state.
Video Imaging Products
3
08/16/2000–LDS.2249-J