LF3311 Datasheet, PDF (19/24 Pages) LOGIC Devices Incorporated – Horizontal / Vertical Digital Image Filter

DEVICES INCORPORATED
LF3311
Horizontal / Vertical Digital Image Filter
Improved Performance
Signal Definitions
Controls Contin-
ued
HACC — Horizontal Accumulator Control
When HACC is HIGH, the horizontal accumulator is enabled for accumulation and the accumulator output
register is disabled for loading. When HACC is LOW, no accumulation is performed and the accumulator
output register is enabled for loading. HACC is latched on the rising edge of CLK.
VACC — Vertical Accumulator Control
When VACC is HIGH, the vertical accumulator is enabled for accumulation and the accumulator output
register is disabled for loading. When VACC is LOW, no accumulation is performed and the accumulator
output register is enabled for loading. VACC is latched on the rising edge of CLK.
HSHEN — Horizontal Shift Enable
HSHEN enables or disables the loading of data into the forward and reverse I/D Registers in the horizontal
filter when the device is in Dimensionally Separate Mode. If the device is configured such that the horizontal
filter feeds the vertical filter, HSHEN also enables or disables the loading of data into the input register
(DIN11-0). If the device is configured such that the vertical filter feeds the horizontal filter and the vertical
limit register is under shift control, HSHEN also enables or disables the loading of data into the vertical limit
register in the vertical Round/Select/Limit circuitry. In Orthogonal Mode, HSHEN also enables or disables
the loading of data into the input register (DIN11-0) and the line buffers in the vertical filter. It is important
to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active
to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit
registers can not be disabled.
When HSHEN is LOW, data is loaded into and shifted through the registers HSHEN controls and the forward
and reverse I/D Registers on the rising edge of CLK. When HSHEN is HIGH, data is not loaded into or
shifted through the registers HSHEN controls and the I/D Registers, and their contents will not be changed.
HSHEN is latched on the rising edge of CLK.
VSHEN — Vertical Shift Enable
VSHEN enables or disables the loading of data into the line buffers in the vertical filter when the device is
in Dimensionally Separate Mode. If the device is configured such that the vertical filter feeds the horizontal
filter, VSHEN also enables or disables the loading of data into the input register (DIN11-0). If the device is
configured such that the horizontal filter feeds the vertical filter and the horizontal limit register is under shift
control, VSHEN also enables or disables the loading of data into the horizontal limit register in the horizontal
Round/Select/Limit circuitry. In Orthogonal Mode, VSHEN also enables or disables the loading of data into
the input register (DIN11-0) and the forward and reverse I/D Registers in the horizontal filter. It is important
to note that in Orthogonal Mode, either HSHEN or VSHEN can disable data loading. Both must be active
to enable data loading in Orthogonal Mode. Also in Orthogonal Mode, the horizontal and vertical limit
registers can not be disabled.
When VSHEN is LOW, data is loaded into and shifted through the registers VSHEN controls and the line
buffers on the rising edge of CLK. When VSHEN is HIGH, data is not loaded into or shifted through the
registers VSHEN controls and the line buffers, and their contents will not be changed. VSHEN is latched
on the rising edge of CLK.
LOGIC Devices Incorporated
Video Imaging Products
19
9/19/05 LDS.3311-C