LF3312 Datasheet, PDF (18/33 Pages) LOGIC Devices Incorporated – 12-Mbit Frame Buffer / FIFO

DEVICES INCORPORATED
LF3312
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Configuration Register Map
Instruction Register 8 (dflt = 10_00_0_111)
7:6 = WIDTH[1:0]
(10: 10 bits)
5:4 = Reserved
(Make equal to 00)
3 = MARK_ACTIVE_RESET (Make equal to 0)
2:0 = OPMODE
(111: Two-Channel Asynchronous FIFO)
Instruction Register 9 (dflt = 00_000_000)
7:6 = TRS_SYNC[1:0]
(00: ignore embedded TRS)
5 = B_FLD
(0: frame sync - use falling F-bit from TRS)
4 = A_FLD
(0: frame sync - use falling F-bit from TRS)
3 = MARK_SEL
(0: use marked address - not user defined address)
2:0 = FLAG_SET
(000: trigger empty, full on 1/80, 79/80)
Instruction Register A (dflt = 00000000)
7 = BSET_catch
(0: setting B pointer does not MARK its new value)
6 = ASET_catch
(0: setting A pointer does not MARK its new value)
5 = RSET_b_sel
(0: RSET is falling edge triggered)
4 = RCLR_b_sel
(0: RCLR is falling edge triggered)
3 = BSET_b_sel
(0: BSET is falling edge triggered)
2 = BCLR_b_sel
(0: BCLR is falling edge triggered)
1 = ASET_b_sel
(0: ASET is falling edge triggered)
0 = ACLR_b_sel
(0: ACLR is falling edge triggered)
Instruction Register B (dflt = 00_00_00_00)
7:4 = BFLAG_CTL
(00: BPE, BPF are part-empty, -full)
3:0 = AFLAG_CTL
(00: APE, APF are part-empty, -full)
Instruction Register C (dflt = 0000_0000)
7:4 = BASE_ADDR
(0000: lowest-address chip in cascade sequence)
3:0 = CASCADE
(0000: single chip - no cascade of multiple chips)
LOGIC Devices Incorporated
Video Imaging Product
18
August 8, 2006 LDS.3312 O