LF3320 Datasheet, PDF (12/24 Pages) LOGIC Devices Incorporated – Horizontal Digital Image Filter

DEVICES INCORPORATED
LF3320
Horizontal Digital Image Filter
the reverse data path. The device must
see a HIGH to LOW transition of
TXFRA/TXFR B in order to switch
LIFOs. If decimating by N,
TXFRA/TXFRB should go LOW once
every N clock cycles. When data
reversal is disabled, the circuitry
functions like an I/D Register. When
feeding interleaved data through the
filter, data reversal should be disabled.
Bit 6 of Configuration Register 1 and
FIGURE 14. DATA REVERSAL
TXFRA/TXFRB
LIFO A
LIFO B
Configuration Register 3 enables or
disables data reversal for Filters A
and B respectively.
Cascading
Three cascade ports are provided to
allow cascading of multiple devices for
more filter taps (see Figure 15).
COUT11-0 of one device should be
connected to DIN11-0 of another device.
ROUT11-0 of one device should be
connected to RIN11-0 of another device.
As many LF3320s as desired may be
cascaded together. However, the
outputs of the LF3320s must be added
together with external adders.
Bit 0 of Configuration Register 5 deter-
mines how the device will send data to
the reverse data path when multiple
LF3320s are cascaded together. If a
LF3320 is the last in the cascade chain,
Bit 0 of Configuration Register 5 should
be set to a “0”. This will cause the data
from the end of the forward data path to
be routed to the beginning of the
reverse data path based on how the
filter is configured (even/odd number
of taps or interleave mode). If a LF3320
is not the last in the cascade chain, Bit 0
of Configuration Register 5 should be set
to a “1”. This will cause RIN11-0 to feed
data to the reverse data path. When
not cascading, Bit 0 of Configuration
Register 5 should be set to a “0”.
Special data routing circuitry is used to
feed the COUT and ROUT output
registers. The data routing circuitry is
required to correctly align data in the
forward and reverse data paths as data
passes from one LF3320 to another.
The COUT and ROUT registers are
loaded with data which is two clock
cycles behind the current output of the
I/D Register just before the ROUT or
COUT register. This correctly accounts
for the extra delays added to the forward
and reverse data paths by the
input/output cascade registers.
FIGURE 15. MULTIPLE LF3320S CASCADED TOGETHER
12
DIN
LF3320
I/D
REGISTERS
I/D
REGISTERS
RIN
ROUT
COUT
DIN
LF3320
I/D
REGISTERS
I/D
REGISTERS
RIN
ROUT
COUT
DIN
LF3320
I/D
REGISTERS
I/D
REGISTERS
RIN
ROUT
COUT
DIN
LF3320
I/D
REGISTERS
I/D
REGISTERS
FILTER
A
FILTER
B
FILTER
A
FILTER
B
FILTER
A
FILTER
B
FILTER
A
FILTER
B
RSL
CIRCUIT
16
RSL
CIRCUIT
16
LF3347
RSL
CIRCUIT
16
RSL
CIRCUIT
16
25
25
RSL
CIRCUIT
16
DATA OUT
128 TAP RESULT
2-12
Video Imaging Products
08/16/2000–LDS.3320-N