LMU217 Datasheet, PDF (1/6 Pages) LOGIC Devices Incorporated – 16 x 16-bit Parallel multiplier

DEVICES INCORPORATED
DEVICES INCORPORATED
LMU217
LMU217 ^{16 x 16-bit Parallel Multiplier}
16 x 16-bit Parallel multiplier
FEATURES
DESCRIPTION
u 25 ns Worst-Case Multiply Time
u Low Power CMOS Technology
u Replaces Cypress CY7C517,
IDT 7217L, and AMD Am29517
u Single Clock Architecture with
Register Enables
u Two’s Complement, Unsigned, or
Mixed Operands
u Three-State Outputs
u 68-pin PLCC, J-Lead
The LMU217 is a high-speed, low
power 16-bit parallel multiplier.
The LMU217 produces the 32-bit prod-
uct of two 16-bit numbers. Data present
at the A inputs, along with the TCA
control bit, is loaded into the A register
on the rising edge of CLK. B data and
the TCB control bit are similarly
loaded. Loading of the A and B
registers is controlled by the ENA and
ENB controls. When HIGH, these con-
trols prevent application of the clock to
the respective register. The TCA and
TCB controls specify the operands as
two’s complement when HIGH, or
unsigned magnitude when LOW.
LMU217 BLOCK DIAGRAM
CLK
ENA
ENB
TCA
A 15-0
16
A REGISTER
TCB
B 15-0/
R15-0
16
B REGISTER
RND is loaded on the rising edge of
CLK, provided either ENA or ENB are
LOW. RND, when HIGH, adds ‘1’ to
the most significant bit position of the
least significant half of the product.
Subsequent truncation of the 16 least
significant bits produces a result
correctly rounded to 16-bit precision.
At the output, the Right Shift control
(RS) selects either of two output formats.
RS LOW produces a 31-bit product
with a copy of the sign bit inserted in the
MSB postion of the least significant half.
RS HIGH gives a full 32-bit product. Two
16-bit output registers are provided to
hold the most and least significant
halves of the result (MSP and LSP) as
defined by RS. These registers are
loaded on the rising edge of CLK, subject
to the ENR control. When ENR is
HIGH, clocking of the result registers is
prevented.
For asynchronous output, these registers
may be made transparent by setting the
feed through control (FT) HIGH and
ENR LOW.
The two halves of the product may be
routed to a single 16-bit three-state
output port (MSP) via a multiplexer.
RND
MSPSEL LOW causes the MSP outputs
to be driven by the most significant half
of the result. MSPSEL HIGH routes the
32
least significant half of the result to the
MSP pins. In addition, the LSP is
RS
FORMAT ADJUST
available via the B port through a sepa-
rate three-state buffer.
16
16
FT
ENR
RESULT
REGISTER
MSPSEL
OEM
16
R 31-16
OEL
16
Multipliers
1
08/16/2000–LDS.217-H